200 Mhz 2.5V Lvds Oscillator; Single-Ended Sma Global Clock Inputs - Xilinx ML628 User Manual

Chapter 1: ML628 Board Features and Operation
four headers. The FPGA JTAG interface can also be driven directly from these headers by
attaching the flying wire JTAG cable to pin 2 of each header.
detailed representation of the isolation jumpers as part of the broader JTAG chain in
Figure
X-Ref Target - Figure 1-9
Table 1-8
Table 1-8: JTAG Isolation Jumpers

200 MHz 2.5V LVDS Oscillator

[Figure
The ML628 board has one 2.5V LVDS differential 200 MHz oscillator (U7) connected to the
FPGA global clock inputs.
The 200 MHz differential clock is enabled by placing two shunts (P, N) across J188 header
pins 1 – 3 and 2 – 4 (LVDS).
Table 1-9: LVDS Oscillator Global Clock Connections

Single-Ended SMA Global Clock Inputs

[Figure
The ML628 board provides two single-ended clock input SMA connectors that can be used
for connecting to an external function generator. The FPGA clock pins are connected to the
SMA connectors as shown in
20
1-8.
U1
FPGA
Figure 1-9: JTAG Isolation Jumpers
indicates the FPGA pin name associated with each jumper.
Reference Designator
J22
J23
J195
J196
1-2, callout 10]
FPGA Pin
AK13 IIO_LVDS_GC_34_P
AK12 IO_LVDS_GC_34_N
1-2, callout 11]
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J196
TCK
J195
TDO
J23
TDI
J22
TMS
FPGA Pin Name
TMS
TDI
TDO
TCK
Table 1-9 lists the FPGA pin connections to the LVDS oscillator.
Net Name U7 Pin
Table 1-10.
Figure 1-9 shows a more
U25
System ACE
Controller
CFGTCK
CFGTDI
CFGTDO
CFGTMS
UG771_c1_09_022211
4
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ML628 Board User Guide
UG771 (v1.0.1) June 28, 2011