Differential Clock Inputs; Dut Socket - Xilinx Virtex-II Pro User Manual

Detailed Description
Table 1-4: OSC Clock Pin Connections

10. Differential Clock Inputs

In addition to the oscillator sockets, there are eight 50
connection to an external function generator. These connect to the DUT clock pads as
shown in
resistors. The differential clock pairings are as shown.
Table 1-5: SMA Clock Pin Connections
Notes:
1. Use these differential clock pairs for the Rocket I/O transceivers. They have been optimized for the
2. These global clocks are not available through the breakout area test points.

11. DUT Socket

The DUT socket contains the user FPGA, referred to as the Device Under Test.
The device must be oriented using the P1 indicator on the board. Failure to insert the
device to the proper orientation can damage the device. To avoid pin damage, always use
the vacuum tool provided when inserting or removing the Virtex-II Pro device. When
Virtex-II Pro Prototype Platform User Guide
UG027 / PN 0402044 (v1.6) October 25, 2002
Clock
Label Name
OSC Socket Top1 GCLK0S
OSC Socket GCLK1P
Bottom 2
OSC Socket GCLK2P
Bottom 1
OSC Socket Top 2 GCLK3S
Table 1-5. They can also be used as differential pairs with 100
FG456
Clock
Label Name
N GCLK1S
P GCLK0P
N GCLK3P
P GCLK2S
N GCLK7S
P GCLK6P
N GCLK5P
P GCLK4S
transceivers.
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1-800-255-7778
FG456 FF672
Pin Clock
Number Name
F12 GCLK0S
E12 GCLK1P
V12 GCLK2P
U12 GCLK3S
FF672
Pin Clock
Number Name
W12 GCLK4P AD13
Y12 GCLK5S AE13
C12 GCLK6P B13
D12 GCLK7S C13
Y11 GCLK7P AE14
W11 GCLK6S AD14
D11 GCLK5P C14
C11 GCLK4S B14
FF1152
Pin Clock
Number Name
E14 GCLK0S
D14 GCLK1P
AB14 GCLK2P
AC13 GCLK3S
Ω
SMA connectors that allow
Ω
termination
FF1152
Pin Clock
Number Name
GCLK4P AK17
GCLK5S AL17
GCLK6P H17
GCLK7S J17
GCLK7P AL18
GCLK6S AK18
GCLK5P J18
GCLK4S H18
R
Pin
Number
E18
D18
AJ17
AH18
Pin
Number
19