200 Mhz 2.5V Lvds Oscillator; Single-Ended Sma Global Clock Inputs - Xilinx ML623 User Manual

X-Ref Target - Figure 1-6
Table 1-4
Table 1-4: JTAG Isolation Jumpers

200 MHz 2.5V LVDS Oscillator

[Figure
The ML623 board has one 2.5V LVDS differential 200 MHz oscillator (U7) connected to the
FPGA global clock inputs.
The 200 MHz differential clock is enabled by placing two shunts (P, N) across J188 header
pins 1 – 3 and 2 – 4 (LVDS).
Table 1-5: LVDS Oscillator Global Clock Connections

Single-Ended SMA Global Clock Inputs

[Figure
The ML623 board provides two single-ended clock input SMA connectors that can be used
for connecting to an external function generator. The FPGA clock pins are connected to the
SMA connectors as shown in
To use these clock inputs, remove jumpers across AFX SEL headers J186 and J187.
ML623 Board User Guide
UG724 (v1.1) September 15, 2010
U1
FPGA
Figure 1-6: JTAG Isolation Jumpers
indicates the FPGA pin name associated with each jumper.
Reference Designator
J22
J23
J195
J196
1-2, callout 10]
FPGA Pin
J9 IO_LVDS_CLK_P
H9 IO_LVDS_CLK_N
1-2, callout 11]
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J196
TCK
J195
TDO
J23
TDI
J22
TMS
FPGA Pin Name
TMS
TDI
TDO
TCK
Table 1-5 lists the FPGA pin connections to the LVDS oscillator.
Net Name U7 Pin
Table 1-6.
Detailed Description
U25
System ACE
Controller
CFGTCK
CFGTDI
CFGTDO
CFGTMS
UG724_c1_06_040610
4
5
17