Chapter 2: Microblaze Architecture; Overview - Xilinx MicroBlaze Reference Manual

MicroBlaze Architecture
This chapter contains an overview of MicroBlaze™ features and detailed information on
MicroBlaze architecture including Big-Endian or Little-Endian bit-reversed format, 32-bit general
purpose registers, virtual-memory management, cache software support, and Fast Simplex Link
(FSL) or AXI4-Stream interfaces.

Overview

The MicroBlaze™ embedded processor soft core is a reduced instruction set computer (RISC)
optimized for implementation in Xilinx
shows a functional block diagram of the MicroBlaze core.
Instruction-side
bus interface
M_AXI_IC
M_ACE_IC
IXCL_M
IXCL_S
M_AXI_IP
IPLB
Bus
IF
ILMB
Optional MicroBlaze feature
MicroBlaze Processor Reference Guide
UG081 (v14.7)
Memory Management Unit (MMU)
UTLB
ITLB
Program
Counter
Special
Purpose
Registers
Branch
Target
Cache
Instruction
Buffer
Instruction
Decode
Figure 2-1: MicroBlaze Core Block Diagram
www.xilinx.com
®
Field Programmable Gate Arrays (FPGAs).
Data-side
bus interface
DTLB
ALU
Shift
Barrel Shift
Multiplier
Divider
FPU
Register File
32 X 32b
Chapter 2
Figure 2-1
M_AXI_DC
M_ACE_DC
DXCL_M
DXCL_S
M_AXI_DP
DPLB
DLMB
Bus
IF
M0_AXIS..
M15_AXIS
S0_AXIS..
S15_AXIS
MFSL 0..15
or
DWFSL 0..15
SFSL 0..15
or
DRFSL 0..15
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