Chapter 2: Product Specification; Hardware Architecture - Xilinx DPU IP Product Manual

Hardware Architecture

The detailed hardware architecture of DPU is shown in Figure 6. After start-up, DPU fetches instructions
from the off-chip memory and parses instructions to operate the computing engine. The instructions
are generated by the DNNDK compiler where substantial optimizations have been performed.
To improve the efficiency, abundant on-chip memory in Xilinx® devices is used to buffer the
intermediate data, input, and output data. The data is reused as much as possible to reduce the
memory bandwidth. Deep pipelined design is used for the computing engine. Like other accelerators,
the computational arrays (PE) take full advantage of the fine-grained building blocks, which includes
multiplier, adder, accumulator, etc. in Xilinx devices.
DPU IP Product Guide
PG338 (v1.2) March 26, 2019

Chapter 2: Product Specification

Processing System (PS)
CPU (DNNDK)
Bus
Fetcher Data Mover
Decoder On-Chip BRAM
Dispatcher BRAM Reader/Writer
PE PE
Programmable Logic (PL)
Figure 6: DPU Hardware Architecture
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Off-Chip Memory
Memory Controller
PE
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