Digital Output; Counter - YASKAWA VIPA System SLIO Manual

VIPA System SLIO
Input delay
12.6.4

Digital output

12.6.4.1 Overview
12.6.4.2 Parametrization in SPEED7 Studio
12.6.4.2.1 'I/O addresses'
Sub module Output address
DI16/DO12 136
137
12.6.5

Counter

12.6.5.1 Overview
12.6.5.2 Parametrization in SPEED7 Studio
12.6.5.2.1 'I/O addresses'
Sub module Input address
Count 816
820
824
828
HB300 | CPU | 013-CCF0R00 | en | 19-30
Here is valid:
n Rising edge: Edge 0-1
n Falling edge: Edge 1-0
n The input delay can be configured per channel in groups of 4.
n An input delay of 0.1ms is only possible with "fast" inputs, which have a max. input
frequency of 100kHz
slow inputs is limited to 0.5ms.
n Range of values: 0.1ms / 0.5ms / 3ms / 15ms
n 12xDC 24V, 0.5A
n Sub module 'DI16/DO12'
Ä Chap. 5.5 'Digital output' page 126
n
Access
BYTE
BYTE
n 4 channels
n Sub module: 'Counter'
Ä Chap. 5.6 'Counting' page 128
n
Access
DINT
DINT
DINT
DINT
Configuration with VIPA SPEED7 Studio
Ä 'X4: Connector' page 45. Within a group, the input delay for
Assignment
Digital output Q+0.0 ... Q+0.7 (X5)
Digital output Q+1.0 ... Q+1.3 (X5)
Assignment
Channel 0: Counter value / Frequency value
Channel 1: Counter value / Frequency value
Channel 2: Counter value / Frequency value
Channel 3: Counter value / Frequency value
Deployment I/O periphery > Counter
279