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Baseboard Requirements
This chapter summarizes the stack-up used for all platform simulations and the placement of
components on the motherboard.
3.1
Platform Stack-Up
Figure 6
shows the recommended 10 layer platform stack-up. All layers are 1 oz copper. The
processor requires 2 oz of copper to deliver power and 2 oz of copper to deliver ground.
Route signal layers as microstrip on layers 1 and 10. Route signal layers as asymmetric stripline on
layers 3, 5, 6 and 8. The signal layers must reference ground on layers 2, 4, 7 or 9 only. Route
signals on layers 5 and 6 orthogonally with respect to routes on signal layers to reduce crosstalk
between the layers.
Intel strongly recommends that system designers use the stack-up shown in
recommendations in
achieve these targeted impedance tolerances; contact your board vendor for these specifics. Intel
encourages platform designers to perform comprehensive simulation analysis to ensure all timing
specifications are met. This is particularly important when a design deviates from the design
guidelines provided.
Ten Layer Stack-up, 50 Ω Board with 5-Mil Traces
Figure 6.
Dielectric 3.8 mil
Core 6.0 mil
Dielectric 6.0 mil
Core 3.8 mil
Dielectric 20.0 mil
Core 3.8 mil
Dielectric 6.0 mil
Core 6.0 mil
Dielectric 3.8 mil
Design Guide
®
®
Intel
Pentium
M Processor and Intel
Table 4
when designing their boards. Intel realizes numerous ways exist to
Layer 1
Signal/Power
Dielectric
Ground
Layer 2
Core
Signal
Layer 3
Signal
Dielectric
Ground
Layer 4
Core
Signal
Signal
Layer 5
Main Dielectric
Layer 6
Signal
Signal
Core
Ground
Layer 7
Dielectric
Signal
Signal
Layer 8
Core
Ground
Layer 9
Dielectric
Layer 10
Signal/Power
®
E7501 Chipset Platform
Baseboard Requirements
Figure 6
and
2.1 mil (1 oz + plating)
1.2 mil (1 oz)
Signal
1.2 mil (1 oz)
1.2 mil (1 oz)
1.2 mil (1 oz)
Signal
1.2 mil (1 oz)
Signal
1.2 mil (1 oz)
Signal
1.2 mil (1 oz)
1.2 mil (1 oz)
2.1 mil (1 oz + plating)
3
37
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