Jtag Debug Module; Jtag Target Connection - Intel NIOS II Owner Reference Manual

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2.7. JTAG Debug Module

The Nios II architecture supports a JTAG debug module that provides on-chip
emulation features to control the processor remotely from a host PC. PC-based
software debugging tools communicate with the JTAG debug module and provide
facilities, such as the following features:
Downloading programs to memory
Starting and stopping execution
Setting breakpoints and watchpoints
Analyzing registers and memory
Collecting real-time execution trace data
Note:
The Nios II MMU does not support the JTAG debug module trace.
The debug module connects to the JTAG circuitry in an Intel FPGA. External debugging
probes can then access the processor via the standard JTAG interface on the FPGA. On
the processor side, the debug module connects to signals inside the processor core.
The debug module has nonmaskable control over the processor, and does not require
a software stub linked into the application under test. All system resources visible to
the processor in supervisor mode are available to the debug module. For trace data
collection, the debug module stores trace data in memory either on-chip or in the
debug probe.
The debug module gains control of the processor either by asserting a hardware break
signal, or by writing a break instruction into program memory to be executed. In both
cases, the processor transfers execution to the routine located at the break address.
The break address is specified with the Nios II Processor parameter editor in Platform
Designer.
Soft processor cores such as the Nios II processor offer unique debug capabilities
beyond the features of traditional, fixed processors. The soft nature of the Nios II
processor allows you to debug a system in development using a full-featured debug
core, and later remove the debug features to conserve logic resources. For the release
version of a product, the JTAG debug module functionality can be reduced, or removed
altogether.
The following sections describe the capabilities of the Nios II JTAG debug module
hardware. The usage of all hardware features is dependent on host software, such as
the Nios II Software Build Tools for Eclipse, which manages the connection to the
target processor and controls the debug process.

2.7.1. JTAG Target Connection

The JTAG target connection provides the ability to connect to the processor through
the standard JTAG pins on the Intel FPGA. This provides basic capabilities to start and
stop the processor, and examine and edit registers and memory. The JTAG target
connection is the minimum requirement for the Nios II flash programmer.
Note:
While the processor has no minimum clock frequency requirements, Intel recommends
that your design's system clock frequency be at least four times the JTAG clock
frequency to ensure that the on-chip instrumentation (OCI) core functions properly.
Nios II Processor Reference Guide
32
2. Processor Architecture
NII-PRG | 2018.04.18

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