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6.2.23
INTRPIN6 - Interrupt Pin
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This register specifies which interrupt pin this device uses.
Table 46.
INTRPIN6 - Interrupt Pin Register
Default
Bit
Access
Value
7:0
RO
6.2.24
BCTRL6 - Bridge Control
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This register provides extensions to the PCICMD6 register that are specific to PCI-PCI
bridges. The BCTRL provides additional control for the secondary interface (i.e., PCI
Express-G) as well as some bits that affect the overall behavior of the "virtual" Host-
PCI Express bridge embedded within processor, e.g., VGA compatible address ranges
mapping.
Table 47.
BCTRL6 - Bridge Control Register (Sheet 1 of 2)
Default
Bit
Access
Value
15:12
RO
11
RO
10
RO
9
RO
8
RO
7
RO
6
RW
®
TM
Intel
Core
i7-620LE/UE, i7-610E, i5-520E and Intel
Datasheet Addendum
102
RST/
PWR
01h
Core
Interrupt Pin (INTPIN)
As a single function device, the PCI Express device specifies INTA
as its interrupt pin. 01h=INTA.
RST/
PWR
0h
Core
Reserved
0b
Core
Discard Timer SERR# Enable (DTSERRE)
Not Applicable or Implemented. Hard wired to 0.
0b
Core
Discard Timer Status (DTSTS)
Not Applicable or Implemented. Hard wired to 0.
0b
Core
Secondary Discard Timer (SDT)
Not Applicable or Implemented. Hard wired to 0.
0b
Core
Primary Discard Timer (PDT)
Not Applicable or Implemented. Hard wired to 0.
0b
Core
Fast Back-to-Back Enable (FB2BEN)
Not Applicable or Implemented. Hard wired to 0.
0b
Core
Secondary Bus Reset (SRESET)
Setting this bit triggers a hot reset on the corresponding PCI
Express Port. This will force the LTSSM to transition to the Hot
Reset state (via Recovery) from L0, L0s, or L1 states.
®
Celeron
Processor Configuration Registers
0/6/0/PCI
3Dh
01h
RO
8 bits
Description
0/6/0/PCI
3E-3Fh
0000h
RO; RW
16 bits
Description
®
Processor P4500, P4505 Series
April 2010
Document Number: 323178-002
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