Clock Supply Map - Fujitsu MB90M405 Hardware Manual

1.9 Clock Supply Map

The clock supply map for this device (Monolith: MB90M405) is shown below.
Clock generator
X0
Oscillator
X1
Divide-by-2
circuit
HCLK MCLK
HCLK: Oscillation clock
MCLK: Main clock (operating clock: clock generated by dividing oscillation clock by 2)
PCLK: PLL clock
GENERAL
Selector
Time-base timer
1 2 3 4
PLL Multiplication circuit
PCLK
Selector
1-15
Timer clock divider
Watchdog timer
Resources
FL Controller
16-bit reload timer
10-bit A/D converter
8-bit serial I/O
6-bit free-run timer
16-bit input capture
16-bit output compare
2
I C Communications interface
2
CPU (F MC-16LX)
ROM/RAM (memory)