Chapter 11 Communication Prescaler; Outline; Block Diagram; Figure 11.2A Block Diagram Of Communication Prescaler - Fujitsu F2MC-16LX MB90580 Series Hardware Manual

Chapter 11:
Communication Prescaler

11.1 Outline

The operation clock for the UART is obtained by dividing the machine clock. UART is designed so that a
constant baud rate can be obtained for a variety of machine clocks by the user of the communication
prescaler. The Clock Division Control Register (CDCR) controls the machine clock division.

11.2 Block Diagram

From Main Clock
Clock
Division
Control
Register
(CDCR)

Figure 11.2a Block diagram of Communication Prescaler

Programmable
Clock
Divider
MD
DIV3
DIV2
DIV1
DIV0
To UART