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18.3.3 Communication Prescaler Control Register0/1
(SDCR0/SDCR1)
This section describes the configuration and functions of the communication
prescaler control register0/1 (SDCR0/SDCR1).
■
Communication prescaler control register0/1 (SDCR0/SDCR1)
The bit configuration of the communication prescaler control register0/1 (SDCR0/SDCR1) is
illustrated below.
SDCR0/SDCR1
ch.0 address: 000029
ch.1
The functions of the bits for the communication prescaler control register0/1 (SDCR0/SDCR1)
are described below.
[bit15] MD: Machine clock divide moDe select
This bit is used to enable operation of the communication prescaler.
0
1
[bit11, bit10, bit9, bit8] DIV3, DIV2, DIV1, DIV0: DIVide3 to 0
These bits determine the division ratio of the machine clocks.
DIV3 to 0
Note:
When changing the clock division ratio, wait for time of 2 division as a clock stabilization time
before the communication is performed.
7
6
MD
-
H
00002D
H
R/W
-
The communication prescaler stops.
The communication prescaler operates.
0000
B
0001
B
0010
B
0011
B
0100
B
0101
B
0110
B
0111
B
CHAPTER 18 EXPANDED I/O SERIAL INTERFACE
5
4
3
2
-
-
DIV3 DIV2 DIV1 DIV0
-
-
R/W
R/W
Division Ratio
Division by 1
Division by 2
Division by 3
Division by 4
Division by 5
Division by 6
Division by 7
Division by 8
1
0
Initial value
0---0000
B
R/W R/W
395
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