Supplement On External Pin And Internal Operation Timing - Fujitsu FR60 Hardware Manual

CHAPTER 14 DMA CONTROLLER (DMAC)
14.3.12 Supplement on External Pin and Internal Operation
Timing
This section provides supplementary information about external pins and internal
operation timing.
■ Minimum Effective Pulse Width of the DREQ Pin Input
Only channels 0 and 1 are applicable for the MB91301 series.
In all transfer modes for burst, step, block, and demand transfers, the minimum width required is
five system clock cycles (5 cycles of external bus clock CLKT).
Note:
DACK output does not indicate acceptance of DREQ input. DREQ input is always accepted if DMA
is enabled but transfer has not started. Therefore, it is not necessary to retain DREQ input until
DACK output is asserted (except in demand transfer mode).
■ Negate Timing of the DREQ Pin Input when a Demand Transfer Request is Stopped
❍ For 2-cycle transfer
For a demand transfer, be sure to set an address in an external area for the transfer source, the
transfer destination, or both.
If the transfer type is external → external:
•
Use the DREQ negation sense timing so that it is placed prior to the write strobe negation
timing by a single cycle or more. There are following measures for achieving this:
- Make the DREQ negation timing by a single cycle or more with the adjustment on the
external I/O side or external glue logic side.
- Increase the wait value from the current value by a single cycle or more by using the auto
wait capability in the external bus controller provided with the FR family.
If DREQ is negated after the period, the next transfer may be executed.
If the transfer type is external → internal:
•
Negate before the last sense timing of the clock in the L section of the external RD pin output
when accessing the transfer source for the last DMA transfer (Section where DACK = "L"
and RD = "L"). If DREQ is negated later than this, a DMA request may be sensed, resulting
in negation until the next transfer
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