Table 4.2.2 Port 0 And 1 Pin State (Single-Chip Mode) - Fujitsu F2MC-8L MB89620 Series Hardware Manual

4.2 Ports 0 and 1
4.2.2 Operation of Ports 0 and 1
This section describes the operations of the ports 0 and 1 in single-chip mode.
n Operation of Ports 0 and 1 (Single-chip Mode)
Operation as an output port
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• Setting the corresponding DDR0 or DDR1 register bit to "1" sets a pin as an output port.
• When a pin is set as an output port, the output buffer is "ON" and the pin outputs the data
stored in the output latch.
• Writing data to the PDR0 and PDR1 registers stores the data in the output latch and outputs
the data directly to the pin.
• Reading the PDR0 or PDR1 register returns the pin value ("0" or "1", the same value as the
output latch).
Note: As the bit manipulation instructions (SETB and CLRB) read the output latch data rather than the pin
level, the instructions do not change the output latch values for bits other than the bit being set or
cleared.
Operation as an input port
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• Setting the corresponding DDR0 or DDR1 register bit to "0" sets a pin as an input port.
• When a pin is set as an input port, the output buffer is "OFF" and the pin goes to the high-
impedance state.
• Writing data to the PDR0 and PDR1 registers stores the data in the output latch but does not
output the data to the pin.
• Reading the PDR0 or PDR1 register returns the pin value ("0" or "1").
Operation at reset
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• Resetting the CPU initializes the DDR0 and DDR1 register values to "0". This sets all output
buffers "OFF" (all pins become input ports) and sets the pins to the high-impedance state.
• The PDR0 and PDR1 registers are not initialized by a reset. Therefore, to use as output
ports, the output data must be set in the PDR0 and PDR1 registers before setting the
corresponding DDR0 or DDR1 register bits to output mode.
Operation in stop mode
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The pins go to the high-impedance state if the pin state specification bit in the standby control
register (STBC: SPL) is "1" when the device changes to stop mode. This is achieved by forcibly
setting the output buffer "OFF" regardless of the DDR0 and DDR1 register values.
Table 4.2.2 lists the port 0 and 1 pin states.

Table 4.2.2 Port 0 and 1 Pin State (Single-chip Mode)

Pin name
P00/AD0 to P07/AD7
P10/A08 to P17/A15
SPL
MOD0, MOD1: Mode pins
Hi-z
Note: Pins with a pull-up resistor (optional) go to the "H" level (pull-up state) rather than to the high-
impedance state when the output buffer is "OFF".
MB89620 series
Normal operation
sleep mode
stop mode (SPL=0)
General-purpose I/O ports
: Pin state specification bit in the standby control register (STBC)
: High impedance
Stop mode
(SPL=1) (MOD0, MOD1 = V
Hi-z
CHAPTER 4 I/O PORTS
Reset
, V )
SS SS
Hi-z
93