Sampled Instruction Address Register (Sia) - IBM PowerPC 604 User Manual

Bits MMCR0[26-31] are used for selecting events associated with PMC2. These settings are
shown in Table 2-6.
Table 2-6. Selectable Events-PMC2
MMCR0[26-31]
Description
Select Encoding
000000 Nothing
00 0001
Processor cycles
00 0010 Number cl Instructions completed
00 0011 RTCSELECT bit transition
00 0100 Number cl instructions dispatched
00 0101 Number cl cycles a load miss takes
00 0110
Data cache misses
00 0111
Instruction
112
misses
00 1000
Branches completed
00 1001
Number cl reservations successfully obtained (STCX succeeded)
001010
Number cl mfspr instructions dispatched
00 1011
Number cl lcbl instructions
00 1100
Number cl lsync instructions
00 1101
Branch unit produced result
00 1110
SCIUO produced result
00 1111 MCIU produced result
01 0000
Instructions dispatched to the branch unit
01 0001
Instructions dispatched to the SCIUO
01 0010
Number cl loads completed
01 0011
Instructions dispatched to the MCIU
01 0100
Number cl snoop hit occurred
2.1.2.4.3 Sampled Instruction Address Register (SIA)
The two address registers contain the addresses of the data or the instruction that caused a
threshold-related performance monitor interrupt. For more information on
threshold-related interrupts, see Section 9.1.2.2, ''Threshold Events."
The SIA contains the effective address of an instruction executing at or around the time that
the processor signals the performance monitor interrupt condition. If the performance
monitor interrupt was triggered by a threshold event, the SIA contains the exact instruction
that caused the counter to become negative. The instruction whose effective address is put
in the SIA is called the sampled instruction.
Chapter 2. PowerPC 604 Processor Programming Model
2-15
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