IBM PowerPC 604 User Manual page 9

Paragraph
Number
2.3.4.6.2
2.3.4.7
2.3.5
2.3.5.1
2.3.5.2
2.3.5.3
2.3.5.3.1
2.3.5.4
2.3.6
2.3.6.l
2.3.6.2
2.3.6.3
2.3.6.3.1
2.3.6.3.2
2.3.6.3.3
2.3.7
CONTENTS
Tltle
Page
Number
Move to/from Special-Purpose Register Instructions (UISA) ............... 2-47
Memory Synchronization Instructions-VISA ......................................... 2-47
PowerPC VEA Instructions ........................................................................... 2-48
Processor Control Instructions-VEA ...................................................... 2-48
Memory Synchronization Instructions-VEA .......................................... 2-49
Memory Control Instructions-VEA ........................................................ 2-50
User-Level Cache Instructions-VEA .................................................. 2-50
Optional External Control Instructions ...................................................... 2-52
PowerPC OEA Instructions ........................................................................... 2-52
System Linkage Instructions-DEA ......................................................... 2-52
Processor Control Instructions-OBA ...................................................... 2-52
Memory Control Instructions-DEA ........................................................ 2-54
Supervisor-Level Cache Management Instruction-(OEA) ................. 2-54
Segment Register Manipulation Instructions (OEA) ............................. 2-55
Translation Lookaside Buffer Management lnstructions-(OEA) ....... 2-55
Recommended Simplified Mnemonics .......................................................... 2-57
Chapter 3
Cache and Bus Interface Unit Operation
3.1 Data Cache Organization ..................................................................................... 3-3
3.2 Instruction Cache Organization ........................................................................... 3-4
3.3 MMUs/Bus Interface Unit ................................................................................... 3-5
3.4 Memory Coherency Actions ................................................................................ 3-8
3.4.1 604-Initiated Load and Store Operations ......................................................... 3-8
3.5 Sequential Consistency ........................................................................................ 3-9
3.5.1 Sequential Consistency Within a Single Processor ......................................... 3-9
3.5.2 Weak Consistency between Multiple Processors ............................................ 3-9
3.5.3 Sequential Consistency Within Multiprocessor Systems .............................. 3-10
3.6 Memory and Cache Coherency .......................................................................... 3-10
3.6.1 Data Cache Coherency Protocol .................................................................... 3-11
3.6.2 Coherency and Secondary Caches ................................................................. 3-13
3.6.3 Page Table Control Bits ................................................................................. 3-13
3.6.4 MESI State Diagram ...................................................................................... 3-13
3.6.5 Coherency Paradoxes in Single-Processor Systems ...................................... 3-14
3.6.6 Coherency Paradoxes in Multiple-Processor Systems ................................... 3-15
3.7 CacheConfiguration .......................................................................................... 3-15
3.8 Cache Control Instructions ................................................................................ 3-16
3.8.1 Instruction Cache Block Invalidate (icbi) ...................................................... 3-16
3.8.2 Instruction Synchronize (isync) ..................................................................... 3-17
3.8.3 Data Cache Block Touch (debt) and
Data Cache Block Touch for Store (dcbtst) .............................................. 3-17
3.8.4 Data Cache Block Set to Zero (dcbz) ............................................................ 3-17
vi PowerPC 604 RISC Microprocessor User's Manual