Integer Store Instructions - IBM PowerPC 604 User Manual

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Table 2-20. Integer Load Instructions (Continued)
Name
Mnemonic Operand syntax
Load Hall Word and Zero with Update lhzu rD,d(rA)
Load Half Word and Zero with Update Indexed
lhzux rD,rA,rB
Load Hall Word Algebraic Iha rD,d(rA)
Load Hall Word Algebraic Indexed lhax rD,rA,rB
Load Hall Word Algebraic with Update lhau rD,d(rA)
Load Hall Word Algebraic with Update Indexed lhaux rD,rA,rB
Load Word and Zero
lwz rD,d(rA)
Load Word and Zero Indexed lwzx
rD,rA,rB
Load Word and Zero with Update
lwzu rD,d(rA)
Load Word and Zero with Update Indexed
lwzux rD,rA,rB
2.3.4.3.4 Integer Store Instructions
For integer store instructions, the contents of rS are stored into the byte, half word, word
or double word in memory addressed by the EA (effective address). Many store instructions
have an update form, in which r A is updated with the EA. For these forms, the following
rules apply:
• If r A
-::J:.
0, the effective address is placed into r A.
• If rS
=
r A, the contents of register rS are copied to the target memory element, then
the generated EA is placed into rA (rS).
The PowerPC architecture defines store with update instructions with r A= 0 as an invalid
form. In addition, it defines integer store instructions with the CR update option enabled
(Re field, bit 31, in the instruction encoding
=
1) to be an invalid form. Table 2-21
summarizes the integer store instructions.
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PowerPC 604 RISC Microprocessor User's Manual