IBM PowerPC 604 User Manual page 73

- SPRGO-SPRG3. The SPRGO-SPRG3 registers are provided for operating
system use. See "SPRGO-SPRG3," in Chapter 2, "PowerPC Register Set," of
The Programming Environments Manual for more information.
- DSISR. The DSISR register defines the cause of OSI and alignment
exceptions. See "DSISR," in Chapter 2, "PowerPC Register Set," of The
Programming Environments Manual for more information.
-
- Machine status save/restore register 0 (SRRO).
The
SRRO register is used to
save machine status on exceptions and to restore machine status when an
rfi
instruction is executed. See "Machine Status Save/Restore Register 0
(SRRO)," in Chapter 2, "PowerPC Register Set," of The Programming
Environments Manual for more information.
- Machine status save/restore register 1 (SRRl ). The SRRl register is used to
save machine status on exceptions and to restore machine status when an rfi
instruction is executed. See "Machine Status Save/Restore Register 1
(SRRl ),'' in Chapter 2, "Power PC Register Set," of The Programming
Environments Manual for more information.
- Miscellaneous registers
- Time Base (TB). The TB is a 64-bit structure that maintains the time of day
and operates interval timers. The TB consists of two 32-bit registers-time
base upper (TBU)
and
time base lower (TBL). Note that the time base
registers can
be
accessed by both user- and supervisor-level instructions. See
"T°IDle Base Facility (TB)-OEA,'' in Chapter 2, "PowerPC Register Set,'' of
The Programming Environments Manual for more information.
- Decrementer register (DEC). This register is a 32-bit decrementing counter
that provides a mechanism for causing a decrementer exception after a
programmable delay; the frequency is a subdivision of the processor clock.
See "Decrementer Register (DEC),'' in Chapter 2, "PowerPC Register Set,'' of
The Programming Environments Manual for more information.
Implementation Note-In
the
604, the decrementer register is decremented
at a speed that is one-fourth
the
speed of the bus clock.
- Data address breakpoint register (DABR)-This optional register can
be
used
to cause a breakpoint exception to occur if a specified data address is
encountered. See "Data Address Breakpoint Register (DABR)," in Chapter 2,
"PowerPC Register Set,'' of The Programming Environments Manual for
more information.
- External access register (EAR). This optional register is used in conjunction
with
the
eciwx and ecowx instructions. Note that
the
EAR register and the
eciwx and ecowx instructions are optional in
the
PowerPC architecture
and
may not
be
supported in all Power PC processors that implement the OBA. See
"External Access Register (EAR),'' in Chapter 2, "PowerPC Register Set,'' of
The Programming Environments Manual for more information.
Chapter 2.. PowerPC 604 Proce880r Programming Model 2-7