Using Data Bus Write Only - IBM PowerPC 604 User Manual

Boundary scan description language (BSDL) files for the 604 and other PowerPC
microprocessors are available in the RISC support area of the Motorola Freeware Data
Services bulletin board system. The bulletin board system, located in Austin, Texas, can be
reached at (512) 891-3733; the connecting terminal or terminal emulator should be
configured with 8-bit data, no parity, and one start and one stop bit. Asynchronous
transmission rates to 14.4K bits per second are supported
8.11 Using Data Bus Write Only
The 604 supports split-transaction pipelined transactions. It supports a limited out-of-order
capability for its own pipelined transactions through the data bus write only (DBWO)
signal. When recognized on the clock of a qualified DBG, the assertion of DBWO directs
the 604 to perform the next pending data write tenure (if any), even if a pending read tenure
would have normally been performed because of address pipelining. The DBWO does not
change the order of write tenures with respect to other write tenures from the same 604. It
only allows that a write tenure be performed ahead of a pending read tenure from the same
604.
In general, an address tenure on the bus is followed strictly in order by its associated data
tenure. Transactions pipelined by the 604 complete strictly in order. However, the 604 can
run bus transactions out of order only when the external system allows the 604 to perform
a cache line snoop push out operation (or other write transaction, if pending in the 604 write
queues) between the address and data tenures of a read operation through the use of
DBWO. This effectively envelopes the write operation within the read operation.
Figure 8-29 shows how the DBWO signal is used to perform an enveloped write
transaction.
Read Address Write Address
Enveloped Write
Transaction
Write Data Read Data
~
(2)"""""" _ _ _ _ _ ....,(1),...._ _ _ _ _ _ _
ucu
L.J LJ
nm --,
11 .... _ _ _ _ _
__.r
'D'BWC
~
Figure 8-29. Data Bus Write Only Transaction
Chapter 8. System Interface Operation
8-53