Tlb Invalidation - IBM PowerPC 604 User Manual

the page index, EA10-EA13 (in addition to theAPI bits of the PTE). Formats for the PTE
are given in "PTE Format for 32-Bit Implementations," in Chapter 7, "Memory
Management," of
The Programming Environments Manual.
Software does not have direct access to the TLB arrays, except to invalidate an entry with
the tlbie instruction.
Each set of TLB entries is associated with one LRU bit, which is accessed when those
entries in the same set are indexed. LRU bits are updated whenever a TLB entry is used or
after the entry is replaced. Invalid entries are always the first to be replaced.
Although both MMUs can be accessed simultaneously (both sets of segment registers and
TLBs can be accessed in the same clock), when there is an exception condition, only one
exception is reported at a time.
Although address translation is disabled on a reset condition, the valid bits of the BAT array
and TLB entries are not automatically cleared. Thus, TLB entries must be explicitly cleared
by the system software (with the tlbie instruction) before the valid entries are loaded and
address translation is enabled Also, note that the segment registers do not have a valid bit,
and so they should also be initialized before translation is enabled.
5.4.3.2 TLB Invalidation
The 604 implements the optional tlbie and tlbsync instructions, which are used to
invalidate TLB entries. The execution of the tlbie instruction always invalidates four
entries-both the ITLB entries indexed by EA14-EA19 and both the indexed entries of the
DTLB.
Execution of the tlbie instruction causes all entries in the congruence class corresponding
to
the specified EA to be invalidated in the processor executing the instruction and also in
the other processors attached to the same bus by causing a TLB invalidate broadcast
operation on the bus as described in Section 7 .2.4, "Address Transfer Attribute Signals."
A TLB invalidate broadcast operation is an address-only transaction issued by a processor
when it executes a tlbie instruction. The address transmitted as part of this transaction
contains bits 12-19 of the EA in their correct respective bit positions.
When a snooping 604 detects a TLB invalidate operation on the bus, it accepts the operation
only if no TLB invalidation is being performed by this processor and all processors on the
bus accept the operation (ARTRY is not asserted). Once accepted, the TLB invalidation is
performed unless the processor is executing a multiple/string instruction, in which case the
TLB invalidation is delayed until the instruction has completed Note that a 604 processor
can only have one TLB invalidation operation pending internally. Thus if the 604 has a
pending TLB invalidate operation, it asserts the ARTRY snoop status in response to another
TLB invalidate operation on the bus. Detected TLB invalidate operations on the bus and
the execution of the tlbie instruction both cause a congruence-class invalidation on both
instruction and data TLBs.
5·26 PowerPC 604 RISC Microprocessor User's Manual