IBM PowerPC 604 User Manual page 144

Table 3-4. Response to Bus Transactions (Continued)
Transaction
Response
Read-with-intent-to- The RWITM transaction Is issued to acquire exclusive use of a memory location for the
modHy (RWITM) purpose of modifying it. One example is a processor that writes to a block that is not
RWITMatomlc
currently in its cache. When GBL is asserted, RWITM transactions on the bus cause the
processors to take the following snoop actions:
• If the addressed block is not in the cache, it takes no action.
• If the addressed block Is In the cache In the Sor Estate, the processor changes the
state al
that block In the cache to I.
• If the addressed block is present in the cache In the XM state, then the 60x asserts
both the ARTRY and the SHARED snoop status signals, pushes the dirty block
out
al
the cache and changes the state of that block In the cache from XM to INV.
RWITM atomic appears on the bus In response to the stwcx. instruction and receives
the same snooping treatment as RWITM.
TLBSYNC This TLB synchronize operation is an address-only transaction placed onto the bus by a
604 when
it
executes a tlbsync Instruction.
When the TLBSYNC bus operation is detected by a snooping 604, the 604 asserts the
ARTRY
snoop status
if
any operations based on an invalidated TLB are pending.
TLB invalidate A TLB invalidate transaction Is an address-only transaction Issued by a processor when
it executes a tlble Instruction. The address transmitted as part al this transaction
contains bits 12-19 of the EA in their correct respective
bit
positions.
In response to a TLB Invalidate operation, snooping processors invatidate the entire
congruence class In any TLBs associated with the specified EA. In addition, a snooping
604 also asserts the
ARTRY
snoop status when
It has
a pending TLB invalidate
operation, and a second TLB invalidate operation Is detected.
For more information on
the
tlble Instruction, see Section 2.3.6.3.3, "Translation
Lookaside Buffer Management lnstructions-(OEA)."
VO
reply
The 110 reply operation is part al the direct-store operation. It serves as the final bus
operation In the series al bus operations that service a direct-store operation.
EIEIO
An EIEIO operation is put onto the bus as a result of executing an elelo instruction. The
elelo instruction enforces ordered execution of accesses to noncacheable memory. The
604s Internally enforce ordering of such accesses with respect to the elelo instruction in
that noncacheable accesses due to instructions that occur before the alelo Instruction in
the program order are placed on the bus before any noncacheable accesses that result
from Instructions that occur after the elelo Instruction with the EIEIO bus operation
separating the two sets of bus operations.
If the system Implements a mechanism that allows reordering of noncacheable
requests, the appearance of an EIEIO operation should cause it to force ordering
between accesses that occurred before and those that occur after.
SYNC The sync instruction generates an address-only transaction, which the 604 places onto
the bus.
When a 604 detects a SYNC operation on the bus, it asserts the
ARTRY
snoop status if
any other snooped cache operations are pending in the device.
Read-with-no-intent-to- A RWNITC operation is issued by a bus-attached device as TT(4,0-3)
=
Ob10101-llke
cache (RWNITC)
a read, but with TT4
=
1). The 604 snoops this operation and If It gets a cache hit on a
block marked M, II writes the block back to memory and marks It E.
This operation is useful for a graphics adapter that reads display data from memory.
This data may be in the processor's cache and may be updated frequently. Because the
adapter does not cache the data, the processor need not leave the block in the S state,
requiring a bus operation to regain exclusive access.
Chapter 3. Ceche and Bua Interface Unit Operation
3-21