Coherency Paradoxes In Single-Processor Systems - IBM PowerPC 604 User Manual

Bus Transactions
RH
=
Read hit
(D
=
Snoop push
RMS
=
Read miss, shared
RME
=
Read miss, exclusive
@
=
Invalidate transaction
WH
=
Write hit
WM
=
Write miss
ffi
=
Read-with-intent-to-modify
SHR
=
Snoop hit on a read
SHW
=
Snoop hit on a write or
(!)
=
Read
read-with-intent-to-modify
Figure
3-6.
MESI C&che Coherency Protocol-State Diagram (WIM
=
001)
Table 3-6 gives a detailed list of MESI transitions for various operations and WIM bit
settings.
3.6.5 Coherency Paradoxes in Single-Processor Systems
The following coherency paradoxes can be encountered within a single processor:
• Load or store operations to a page with WIM
=
ObOll and a cache hit occurs.
Caching was supposed to be inhibited for this page. Any load operation to a cache-
inhibited page that hits in the cache presents a paradox to the processor. The 604
ignores the data in the cache and the state of the cache block is unchanged.
• Store operation to a page with WIM
=
OblOX and a cache hit on a modified cache
block occurs. This page was marked as write-through yet the processor was given
access to the cache (write-through page are always main memory). Any store
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PowerPC 604 RISC Microprocessor User's Manual