Access To Direct-Store Segments - IBM PowerPC 604 User Manual

3.11 Access to Direct-Store Segments
The 604 supports both memory-mapped and 1/0-mapped access to 1/0 devices. In addition
to the high-performance bus protocol for memory-mapped I/0 accesses, the 604 provides
the ability
to
map memory areas to the direct-store interface (SR[T]
=
1) with the following
two kinds of operations:
• Direct-store operations. These operations are considered to address the noncoherent
and noncacheable direct-store; therefore, the 604 does not maintain coherency for
these operations, and the cache is bypassed completely.
• Memory-forced direct-store operations. These operations are considered to address
memory space and are therefore subject to the same coherency control as memory
accesses. These operations are global memory references within the 604 and are
considered to be noncacheable.
Cache behavior (write-back, cache-inhibition, and enforcement of MESI coherency) for
these operations is determined by the settings of the WIM bits.
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PowerPC 604 RISC Microprocessor User's Manual