IBM PowerPC 604 User Manual page 346

Figure 8-20 shows the use of data-delay controls with burst transfers. Note that all
bidirectional signals are three-stated between bus tenures. Note the following:
• The first data beat of bursted read data (clock 3) is the critical quad word.
• The write burst shows the use of TA signal negation to delay the third data beat.
• The final read burst shows the use of DRTRY on the third data beat.
• The address for the third transfer is delayed until the first transfer completes.
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Figure 8·20. Burst Transfers with Data Delay Controls
PowerPC 604 RISC Microprocessor User's Manual