Address Translation Mechanisms - IBM PowerPC 604 User Manual

5.1.3 Address Translation Mechanisms
Power.PC processors support the following four types of address translation:
• Page address translation-translates the page frame address for a 4-Kbyte page size
• Block address translation-translates the block number for blocks that range in size
from 128 Kbyte to 256 Mbyte.
• Direct-store interface address translation-used to generate direct-store interface
accesses on the external bus; not optimized for performance-present for
compatibility only.
• Real addressing mode address translation-when address translation is disabled, the
physical address is identical to the effective address.
Figure 5-4 shows the four address translation mechanisms provided by the MMUs. The
segment descriptors shown in the figure control both the page and direct-store interface
address translation mechanisms. When an access uses the page or direct-store interface
address translation, the appropriate segment descriptor is required. In 32-bit
implementations, one of the 16 on-chip segment registers (which contain segment
descriptors) is selected by the four highest-order effective address bits.
A control bit in the corresponding segment descriptor then determines
if
the access is to
memory (memory-mapped) or to the direct-store interface space. Note that the direct-store
interface is present only for compatibility with existing 1/0 devices that used this interface.
When an access is determined to be to the direct-store interface space, the implementation
invokes an elaborate hardware protocol for communication with these devices. The
direct-store interface protocol is not optimized for performance, and therefore, its use is
discouraged. The most efficient method for accessing 1/0 devices is by memory-mapping
the 1/0 areas.
For memory accesses translated by a segment descriptor, the interim virtual address is
generated using the information in the segment descriptor. Page address translation
corresponds to the conversion of this virtual address into the 32-bit physical address used
by the memory subsystem. In most cases, the physical address for the page resides in an
on-chip TLB and is available for quick access. However,
if
the page address translation
misses in an on-chip TLB, the MMU causes a search of the page tables in memory (using
the virtual address information and a hashing function) to locate the required physical
address.
Block address translation occurs in parallel with page and direct-store segment address
translation and is similar to page address translation; however, fewer higher-order effective
address bits are translated into physical address bits (more lower-order address bits (at least
17) are untranslated to form the offset into a block). Also, instead of segment descriptors
and a TLB, block address translations use the on-chip BAT registers as a BAT array. If an
effective address matches the corresponding field of a BAT register, the information in the
BAT register is used to generate the physical address; in this case, the results of the page
translation and the direct-store translation (occurring in parallel) are ignored.
Chapter 5. Memory Management
5-9