Bus Request (Br)-Output - IBM PowerPC 604 User Manual

7.2.1.1 Bus Request (BR)-Output
The bus request (BR) signal is an output signal on the 604. Following are the state meaning
and timing comments for the BR signal.
State Meaning Asserted-Indicates that the 604 is requesting mastership of the
address bus. Note that BR may be asserted for one or more cycles,
and then deasserted due to an internal cancellation of the bus request
(for example, due to the loss of a memory reservation). See
Section 8.3.1, "Address Bus Arbitration."
Negated-Indicates that the 604 is not requesting the address bus.
The 604 may have no bus operation pending, it may be parked, or the
ARTRY input was asserted on the previous bus clock cycle.
Timing Comments Assertion-Occurs when a bus transaction is needed and the 604
does not have a qualified bus grant. This may occur even if the three
possible pipeline accesses have occurred.
Negation-Occurs for at least one bus clock cycle after an accepted,
qualified bus grant (see BG and ABB), even if another transaction is
pending. It is also negated for at least one bus clock cycle when the
assertion of ARTRY is detected on the bus, with the exception of the
bus master that asserted ARTRY due to the need to perform a cache
line push.
7 .2.1.2 Bus Grant (lm)-lnput
The bus grant (BG) signal is an input signal on the 604. Following are the state meaning
and timing comments for the BG signal.
State Meaning Asserted-Indicates that the 604 may, with the proper qualification,
assume mastership of the address bus. A qualified bus grant occurs
when
BG
is asserted, ABB and ARTRY are not asserted, and
ARTRY has been negated on the previous cycle. The ABB and
ARTRY signals are driven by the 604 or other bus masters.
If
the 604
is parked, BR need not
be
asserted for the qualified bus grant. See
Section 8.3.1, "Address Bus Arbitration."
Negated- Indicates that the 604 is not the next potential address bus
master.
Timing Comments Assertion-May occur at any time to indicate the 604 is free to use
the
address b11s. After the 604 assumes bus mastership, it does not
check for a qualified bus grant again until the cycle during which the
address bus tenure is completed (assuming ithas another transaction
to
run). The 604 does not accept a BG in the cycles between the
assertion of any TS or XATS through to the assertion of AACK.
7-4
Negation-May occur at any time
to
indicate the 604 cannot use the
bus. The 604 may still assume bus mastership on the bus clock cycle
PowerPC 604 RISC Microprocessor User's Manual