IBM PowerPC 604 User Manual page 432

A
AO-A31 signals, 7-7
AACK signal, 7-16
ABB
signal, 7-5, 8-7
Address bus
address tenure, 8-6, 8-39
address transfer
AO-A31, 7-7
APO-AP3, 7-8
APE, 7-9
signals, 8-12
address transfer attribute
Cl, 7-14
CSEO-CSEl, 7-15
GBL, 7-15
'i'BST,
7-13, 8-13
TC:O-TC2, 7-13,8-17
TSIZO-TSIZ2, 7-11, 8-13
11'0-11'4,7-10,8-13
WT, 7-15
address transfer
start
TS",
7-6
XATS, 7-6
address transfer tennination
MCI{, 7-16
AR1RY, 7-16
SHD, 7-17
tenninating address transfer, 8-18
arbitration signals, 8-7
bus atbitration
ABB, 7-5
BG, 7-4
BR, 7-4
bus parking, 8-11
Address translation,
aee
Memory management unit
Aligned
data
transfer, 8-14
Alignment
exception, 4-17, 5-17
misaligned accesses, 2-17
rules,
2-17
APO-AP3 signals, 7-8
APE signal, 7-9
Atbitration, system bus, 8-10, 8-20
AR1RY signal, 7-16
Atomic memory references
using lwarx/stwcx., 3-19
Index
INDEX
B
BAT registen
BAT, description, 2-6
BG signal, 7-4, 8-7
Bits used to configure cache, 3-15
Block address translation
BAT register initialization, 5-13
block address translation flow, 5-12
selection of
block address translation, 5-9
Boundeclly undefined, definition, 2-21
BR signal, 7-4, 8-7
Branch instructions
address calculation, 2-44
branch instructions, 2-44, A-25
condition register logical, 2-45, A-25
system linkage, 2-46, 2-52, A-26
trap, 2-45, A-26
Branch prediction, 6-2, 6-24
Branch processing unit
instruction timings, 6-25, 6-35
overview, 1-9
Branch resolution, 6-2
Bunt data transfen
64-bit data bus, 8-14
transfen
with
data delays, timing, 8-36
Bus configurations, 8-48, 8-49, 8-50
Bus intetface unit
(BIU)
description, 1-14, 3-5, 6-15
Byte ordering
default, 2-23
c
Cache
bits
used
to
configure cache, 3-15
cache configuration, 3-15
cache integration, 3-3
characteristics, 3-1
data
caches and memory queues, 6-14
MESI state definitions, 3-11
organization, instruction and data, 3-2, 3-3, 3-4
set associativity, 3-4
Cache arbitration, 6-24
Cache block push operation, 3-18, 3-22
Cache cast-out operation, 3-18
lndex-1
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