Processor Configuration Signals; Timebase Enable; Reservation; L2 Intervention - IBM PowerPC 604 User Manual

If detenninistic cycle sequencing is required (for example, in multiple processor systems
operating in lock step), the SRESET signal should be asserted and negated synchronously
with the SYSCLK. signal. The SRESET signal has additional functionality in certain test
modes.
7.2.10 Processor Configuration Signals
The signals described in this section provide inputs for controlling the 604's timebase,
signal drive capabilities, L2 cache access, bus snooping while in nap mode, and PLL
configuration, along with output signals to indicate that a storage reservation has been set,
and that the 604 's internal clocking has stopped.
7.2.10.1 Timebase Enable (TBEN)-lnput
The timebase enable (TBEN) signal is input only on the 604. Following are the state
meanings and timing comments for the TBEN signal.
State
Meaning Asserted-Indicates that the timebase should continue clocking.
This input is essentially a "count enable" control for the timebase
counter.
Negated-Indicates the timebase should stop clocking.
Timing Comments Assertion/Negation-May occur on any cycle.
7 .2.10.2 Reservation (RSRV)-Output
The reservation (RSRV) signal is output only on the 604. Following are the state meaning
and timing comments for the RSRV signal.
State
Meaning Asserted/Negated-Represents the state of the reservation
coherency bit in the reservation address register that is used by the
lwan: and
stwcx.
instructions. See Section 8.9.1, "Support for the
lwarx/stwcx. Instruction Pair."
Timing Comments Assertion/Negation-Occurs synchronously one bus clock cycle
after the execution of an lwan: instruction that sets the internal
reservation condition.
7.2.10.3 L2 Intervention (L2_1NT)-lnput
The L2 intervention (L2_INT) signal is input only on the 604. Following are the state
meanings and timing comments for the L2_INT signal.
State
Meaning
Asserted- Indicates that the current data transaction requires
intervention from other bus masters.
Negated-Indicates that the current data transaction requires no
intervention from other bus masters.
Timing Comments Assertion/Negation-The L2_INT signal is sampled by the 604
concurrently with the first assertion of TA for a given data tenure.
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PowerPC 604 RISC Microproc:eesor User's Manual