IBM PowerPC 604 User Manual page 357

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REQUEST OP
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IMM. OP
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DR
lU\Tll
ADDR+XATC 1
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LASTOP
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7
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s
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REPLY OP
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Figure 8-26. Direct-Store Interlace Load Access Example
Figure 8-27 shows a direct-store store access, comprised of three direct-store operations.
As with the example in Figure 8-26, notice that data is transferred only on the 32 bits of the
DH bus. As opposed to Figure 8-26, there is no request operation since the 604 has the data
ready for the BUC.
The assertion of the TEA signal during a direct-store operation indicates that an
unrecoverable error has occurred. If the TEA signal is asserted during a direct-store
operation, the TEA action will be delayed and following direct-store transactions will
continue until all
data
transfers from direct store segment had been completed.
The
bus
agent that asserts TEA is responsible to assert TEA for every direct-store transaction tenure
including
the
last one.
The
direct-store reply,
under
this case, is not required and will be
ignored by the processor. The processor will
take
a machine check exception after the last
direct-store data tenure has been terminated by the assertion of TEA, and not before.
Chaptw 8.
System
Interface Operation 8-47