Operation Of The System Interface - IBM PowerPC 604 User Manual

Cache lines are selected for replacement based on an LRU (least recently used) algorithm.
Each time a cache line is accessed, it is tagged as the most recently used line of the set.
When a miss occurs, if all lines in the set are marked as valid, the least recently used line
is replaced with the new data. When data to be replaced is in the modified state, the
modified data is written into a write-back buffer while the missed data is being read from
memory. When the load completes, the 604 then pushes the replaced line from the write-
back buffer to main memory in a burst write operation if the memory queue is idle, or at a
later time if other transactions are pending.
8.1.2 Operation of the System Interface
Memory accesses can occur in single-beat (1-8 bytes) and four-beat (32 bytes) burst data
transfers. The address and data buses are independent for memory accesses to support
pipelining and split transactions. The 604 can pipeline as many as three transactions and
has limited support for out-of-order split-bus transactions.
Access to the system interface is granted through an external arbitration mechanism that
allows devices to compete for bus mastership. This arbitration mechanism is flexible,
allowing the 604 to be integrated into systems that implement various fairness and bus-
parking procedures to avoid arbitration overhead.
Typically, memory accesses are weakly ordered-sequences of operations, including
load/store string and multiple instructions, do not necessarily complete in the order they
begin-maximizing the efficiency of the bus without sacrificing coherency of the data. The
604 allows read operations to precede store operations (except when a dependency exists).
In addition, the 604 performs snoop push operations ahead of all other bus operations.
Because the processor can dynamically optimize run-time ordering of load/store traffic,
overall performance is improved.
Note that the Synchronize (sync) or Enforce In-Order Execution of 1/0 ( eieio) instructions
can be used
to
enforce strong ordering.
The following sections describe how the 604 interface operates, providing detailed timing
diagrams that illustrate how the signals interact. A collection of more general timing
diagrams are included as examples of typical bus operations.
Figure 8-2 is a legend of the conventions used in the timing diagrams.
This is a synchronous interface-all 604 input signals are sampled and output signals are
driven on the rising edge of the bus clock cycle (see the 604 hardware specifications for
exact timing information).
8-4
PowerPC 604 RISC Microprocesaor User's Manual