Performance Monitor Counter Registers (Pmcl And Pmc2) - IBM PowerPC 604 User Manual

Table 9-1. Performance Monitor SPRs
SPRNumber spr[5-9)
II
spr[0-4) Register Name Access Level
952 Ob1110111000
MMC RO
Supervisor
953 Ob1110111001 PMC1
Supervisor
954 Ob1110111010 PMC2
Supervisor
955
Ob1110111011
SIA Supervisor
959 Ob1110111111
SDA Supervisor
9.1.1.1 Performance Monitor Counter Registers (PMC1 and PMC2)
PMCl and PMC2 are 32-bit counters that can be programmed to generate interrupt signals
when they are negative. Counters are considered to
be
negative when the high-order bit (the
sign bit) becomes set; they reach the value Ox.8000_0000, that is, all zeros with the most
significant bit, or sign bit, set. However, an interrupt is not signaled unless both
MMCRO[INTCONTROL] and MMCRO[ENINT] are also set.
Note that the interrupts can be masked by clearing MSR[EE]; the interrupt signal condition
may occur with MSR[EE] cleared, but the interrupt is not taken until the EE bit is set.
Setting MMCRO[DISCOUNT] forces the counters to stop counting when a counter
interrupt occurs.
PMCl and PMC2 are SPRs 953 and 954, respectively, and can be read and written to by
using the mfspr and mtspr instructions. Software is expected to use the mtspr instruction
to explicitly set the PMC register to nonnegative values. If software sets a negative value,
an erroneous interrupt may occur. For example, if both MMCRO[INTCONTROL] and
MMCRO[ENINT] are set and the mtspr instruction is used to set a negative value, an
interrupt signal condition may be generated prior to the completion of the mtspr and the
values of the SIA and SDA may not have any relationship to the type of instruction being
counted.
The event that is to be monitored can be chosen by setting the appropriate bits in the
MMCRO[l9-31]. The number of occurrences of these selected events is counted from the
time the MMCRO was set either until a new value is introduced into the MMCRO register
or until a performance monitor interrupt is generated. Table 9-2 and Table 9-3 list the
selectable events for the PMCl and PMC2 registers, respectively, with their appropriate
MMCRO encodings.
9.1.1.1.1 PMC1 Selectable Events
The events counted by PMCl can be divided into two groups.
• Events that can occur only once per cycle. These are the most common.
• Events can have as many as four occurrences per cycle, such as instructions
dispatched per clock.
Chapter 9. Performance Monitor 9-3