Integer Load And Store Address Generation; Register Indirect Integer Load Instructions - IBM PowerPC 604 User Manual

2.3.4.3.2 Integer Load and Store Address Generation
Integer load and store operations generate effective addresses using register indirect with
immediate index mode, register indirect with index mode, or register indirect mode. See
Section 2.3.2.3, "Effective Address Calculation," for information about calculating
effective addresses. Note that in some implementations, operations that are not naturally
aligned may suffer performance degradation. Refer to Section 4.5.6, "Alignment Exception -
(Ox00600)," for additional information about load and store address alignment exceptions.
2.3.4.3.3 Register Indirect Integer Load Instructions
For integer load instructions, the byte, half word, word, or double word addressed by the
EA (effective address) is loaded into rD. Many integer load instructions have an update
form, in which r A is updated with the generated effective address. For these forms, if
rA*" 0 and rA*- rD (otherwise invalid), the EA is placed into rAand the memory element
(byte, half word, word, or double word) addressed by the EA is loaded into rD. Note that
the Power PC architecture defines load with update instructions with operand r A = 0 or
rA = rD as invalid forms.
Implementation Notes-The following notes describe the 604 implementation of integer
load instructions:
• In the PowerPC architecture, the Re bit must be zero for almost
all
load and store
instructions. If the Re bit is one, the instruction form is invalid. These include the
integer load indexed instructions (lbzx, lbzux, lhzx, lhzux, lhax, lhaux, lwzx, and
lwzux). In the 604, executing one of these invalid instruction forms causes CRO to
be set to an undefined value.
• For load with update instructions (lbzu, lbzux, lhzu, lhzux, lhau, lhaux, lwzu,
lwzux, lfsu, lfsux, lfdu, lfdux), when rA = 0 or rA = rD the instruction form is
considered invalid. If r A = 0, the 604 sets GPRO to an undefined value. If r A= rD,
the 604 sets rD to an undefined value.
• The PowerPC architecture cautions programmers that some implementations of the
architecture may execute the Load Half Algebraic (Iha, lhax) instructions with
greater latency than other types of load instructions. This is not the case for the 604.
Table 2-20 summarizes the integer load instructions.
Table 2·20. Integer Load Instructions
Name
Mnemonic Operand Syntax
Load Byte and Zero lbz
rD,d(rA)
Load Byte and Zero Indexed
lbzx rD,rA,rB
Load Byte and Zero with Update lbzu
rD,d(rA)
Load Byte and Zero with Update Indexed lbzux rD,rA,rB
Load Hall Word and Zero
lhz rD,d(rA)
Load Half Word and Zero Indexed lhzx rD,rA,rB
Chapter 2. PowerPC 604 Proceuor Programming Model 2-35