Write-Through Mode; Cache-Inhibited Mode - IBM PowerPC 604 User Manual

If more than one device uses data stored in a page that is in write-back mode, snooping must
be enabled to allow write-back operations and cache invalidations of modified data. The
604 implements snooping hardware to prevent other devices from accessing invalid data.
When bus snooping is enabled, the processor monitors the transactions of the other devices.
For example, if another device accesses a memory location and its memory-coherent
(M)
bit is set, and the 604's on-chip cache has a modified value for that address, the processor
preempts the bus transaction, and updates memory with the cache data.
If
the cache
contents associated with the snooped address are unmodified, the 604 invalidates the cache
block. The other device is then free to attempt an access to the updated memory address.
See Chapter 3, "Cache and Bus Interface Unit Operation," for complete information about
bus snooping.
Write-back mode provides complete cache/memory coherency as well as maximizing
available external bus bandwidth.
6.3.4.2 Write-Through Mode
Store operations to memory in write-through mode always update memory as well as the
on-chip cache (on cache hits). Write-through mode is used when the data in the cache must
always agree with external memory (for example, video memory), or when there is shared
(global) data that may be used frequently, or when allocation of a cache block on a cache
miss is undesirable. Cached data is not automatically written back if that data is from a
memory page marked as write-through mode since valid cache data always agrees with
memory.
Stores to memory that are in write-through mode may cause a decrease in perfonnance.
Each time a store is perfonned to memory in write-through mode, the bus remains busy for
the extra clock cycles required to update memory; therefore, load operations that miss the
cache must wait until the external store operation completes.
6.3.4.3 Cache-Inhibited Mode
If a memory page is specified to be cache-inhibited, data from this page is not cached.
Areas of the memory map can be cache-inhibited by the operating system software. If a
cache-inhibited access hits in the on-chip cache, the corresponding cache block is
invalidated.
If
the line is marked as modified, it is written back
to
memory before being
invalidated.
In summary, the write-back mode allows both load and store operations to use the on-chip
cache. The write-through mode allows load operations to use the on-chip cache, but store
operations cause a memory access and a cache update if the data is already in the cache.
Lastly, the cache-inhibited mode causes memory access for both loads and stores.
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PowerPC 604 RISC Microprocessor User's Manual