IBM PowerPC 604 User Manual page 230

-
Branch
Correction
Fetch Unit
Dispatch Unit
(Four-Instruction
Dispatch)
Instruction Dispatch Buses
GPR Operand Buses
' " - -1: - -
r. - -
1- - - - - . - - - •
I GPR Result Buses I I I
1
1
_ _
.....,_....-1 ....
--+-.--..~l-""i"""
I FPR Operand Buses
I
l
I
,---1.---i
I
I FPR Result Buses
I
Instruction 16-Kbyte Data Cache
Completion Unit 4-Way,
8
Words/Block
Result Status Buses
Result Buses
Operand Buses
Dispatch Buses
Figure 6-1. PowerPC 604 Microprocessor Block Diagram Showing Data Paths
As shown in Table 6-1, effective throughput of more than one instruction per clock cycle
can be realized by the many performance features in the 604 including multiple execution
units that operate independently and in parallel, pipelining, superscalar instruction issue,
dynamic branch prediction, the implementation of two reservation stations for each
execution unit to avoid additional latency due to stalls in individual pipelines, and result
buses that forward results to dependent instructions instead of requiring those instructions
to wait until results become available in the architected registers.
The reservation stations and result buses for the GPRs are shown in Figure 6-2
6-4 PowerPC 604 RISC Mlcroproceasor User's Manual