IBM PowerPC 604 User Manual page 19

Figure
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xvi
ILLUSTRATIONS
Title
Page
Number
Instruction Timing-Instruction Cache Miss (BT AC Hit) .................................. 6-22
Instruction Timing-Branch with BT AC Hit ...................................................... 6-25
Instruction Timing-Branch with BT AC Miss/Decode Correction .................... 6-27
Instruction Timing-Branch with BT AC Miss/Dispatch Correction .................. 6-28
Instruction Timing-Branch with BT AC Miss/Execute Correction .................... 6-29
GPR Rename Register ................................................................................••........ 6-32
SCIU Block Diagram ........................................................................................... 6-36
MCIU Block Diagram .......................................................................................... 6-37
FPU Block Diagram ............................................................................................. 6-38
LSU Block Diagram ............................................................................................. 6-40
Store Queue Structure .......................................................................................... 6-41
PowerPC 604 Microprocessor Signal Groups ........................................................ 7-3
IEEE 1149.1-Compliant Boundary Scan Interface .............................................. 7-30
PowerPC 604 Microprocessor Block Diagram ...................................................... 8-3
Timing Diagram Legend ........................................................................................ 8-5
Overlapping Tenures on the PowerPC 604 Microprocessor Bus for a Single-Beat
Transfer ..•.......................................................................•................................... 8-6
Address Bus Arbitration .............................•.........................................•............... 8-10
Address Bus Arbitration Showing Bus Parking ................................................... 8-11
Address Bus Transfer ..•........................................................................................ 8-12
Snooped Address Cycle with ARTRY ................................................................. 8-19
Data Bus Arbitration ............................................................................................ 8-20
Qualified DBG Generation Following ARTRY ................................................... 8-22
Normal Single-Beat Read Termination ................................................................ 8-25
Normal Single-Beat Write Termination ............................................................... 8-26
Normal Burst Transaction .................................................................................... 8-26
Termination with DRTRY •.................................................................................. 8-27
Read Burst with TA Wait States and DRTRY ..................................................... 8-28
MESI Cache Coherency Protocol-State Diagram (WIM
=
001) ....................... 8-31
Fastest Single-Beat Reads .................................................................................... 8-32
Fastest Single-Beat Writes ................................................................................... 8-33
Single-Beat Reads Showing Data-Delay Controls ............................................... 8-34
Single-Beat Writes Showing Data Delay Controls .............................................. 8-35
Burst Transfers with Data Delay Controls ...................................................•....... 8-36
Use of Transfer Error Acknowledge (TEA) ..............................................•.•........ 8-37
Direct-Store Tenures ........•................................................................................... 8-40
Direct-Store Operation-Packet 0 ........................................................................ 8-43
Direct-Store Operation-Packet 1 ........................................................................ 8-44
1/0 Reply Operation ............................................................................................. 8-45
Direct-Store Interface Load Access Example ...................................................... 8-47
Direct-Store Interface Store Access Example ...................................................... 8-48
Data Transfer in Fast-L2/Data Streaming Mode ................................................... 8-50
Data Bus Write Only Transaction ......................................................................... 8-53
PowerPC 604 RISC Microprocessor User's Manual