Atomic Memory References; Snoop Response To Bus Operations; Cache Reaction To Specific Bus Operations - IBM PowerPC 604 User Manual

3.9.4 Atomic Memory References
The lwarx/stwcx. instruction combination can be used to emulate atomic memory
references. These instructions are described in Chapter 2, "PowerPC 604 Processor
Programming Model."
3.9.5 Snoop Response to Bus Operations
When the 604 is not the bus master, it monitors bus traffic and perfonns cache and memory-
queue snooping as appropriate. The snooping operation is triggered by the receipt of a
qualified snoop request A qualified snoop request is generated by the simultaneous
assertion of the TS and GBL bus signals.
Instruction processing is interrupted for one clock cycle only when a snoop hit occurs and
the snoop state machine determines a push-out operation is required.
The 604 maintains a write queue of bus operations in progress and/or pending arbitration.
This write queue is also snooped in response
to
qualified snoop requests. Note that block-
length (four beat) write operations are always snooped in the write queue; however, single-
beat writes are not snooped. Coherency for single-beat writes is maintained through the use
of cache operations that are broadcast with the write on the system interface or the
lwarx/stwcx. instructions.
The 604 drives two snoop status signals (ARTRY and SHD) in response
to
a qualified
snoop request that hits. These signals provide infonnation about the state of the addressed
block for the current bus operation. For more infonnation about these signals, see
Chapter 7, "Signal Descriptions."
3.9.6 Cache Reaction to Specific Bus Operations
There are several bus transaction types defined for the 604 bus. The 604 must snoop these
transactions and perfonn the appropriate action to maintain memory coherency; see
Table 3-4. For example, because single-beat write operations are not snooped when they
are queued in the memory unit, additional operations such as flush or kill operations, must
be broadcast when the write is passed to the system interface to ensure coherency.
A processor may assert ARTRY for any bus transaction due
to
internal conflicts that prevent
the appropriate snooping. In general, if ARTRY is not asserted, each snooping processor
must take full ownership for the effects of the bus transaction with respect to the state of
the processor.
The transactions in Table 3-4 correspond
to
the transfer type signals TTO-TT4, which are
described in Section 7.2.4.1, "Transfer Type (TTO-TT4)."
Chapter 3. Cache and Bus Interface Unit Operation
3-19