Instruction Dispatch And Completion Considerations - IBM PowerPC 604 User Manual

resolved. If the prediction is correct, there is no penalty. If the prediction is incorrect,
shadow registers are restored from the saved values so instructions fetched from the correct
path can be dispatched and executed. When the branch instruction completes, architected
registers are updated
6.4.6 Instruction Dispatch and Completion Considerations
The 604's ability to dispatch instructions at a
peak
rate of four per cycle is affected by
availability of such resources as execution units, destination rename registers, and
completion buff er entries. To avoid dispatch unit stalls due to instruction data
dependencies, each execution unit has two reservation stations. If a data dependency could
prevent an instruction from beginning execution, that instruction is dispatched
to
the
reservation station associated with its execution unit, clearing the dispatch unit. When the
data that the operation depends upon is returned via a cache access or as a result of a
previous operation, execution begins during the cycle after the rename register is updated.
If
the second instruction in the dispatch unit requires the same execution unit, that
instruction is not dispatched until the first instruction completes execution.
Instructions are dispatched
to
reservation stations in order, but from the perspective of the
overall program flow, instructions can execute out of order. The following aspects of the
604's support for out-of-order execution should be noted:
• The BPU, FPU, and LSU each have two-entry in-order reservation stations. These
stations allow instructions to clear the dispatch stage even though operands may not
yet be available for execution to occur. The BPU, FPU, and LSU instructions may
execute out of order with respect to one another and
to
other execution units, but the
BPU, FPU, and LSU instructions pass through their respective reservation stations
and pipelines in program order.
• Each integer unit has a two-entry out-of-order reservation station which allows
integer instructions to execute out-of-order within each execution as well as with
respect to instructions in other execution units.
The completion unit can track instructions from dispatch through execution and ensure that
they are completed in program order. In-order completion ensures the correct architectural
state. when the 604 must recover from a mispredicted branch, or any other exception or
interrupt.
The rate of instruction completion is unaffected by the 604 's ability to write the instruction
results from
the
rename registers
to
the architecturally defined registers when the
instruction is retired. The 604 can perfonn two write-back operations from each of the
rename registers
to
the register files (CR, GPRs, and FPRs) each clock cycle.
Due to the 604's out-of-order execution capability,
the
in-order completion of instructions
by the completion unit provides a precise
e~ception
mechanism. All program-related
exceptions are signaled when the instruction causing the exception has reached the last
position in the completion buffer. All prior instructions are allowed to complete and write
back before the exception is taken.
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PowerPC 604 RISC Microprocessor User's Manual