IBM PowerPC 604 User Manual page 18

Figure
Number
1-1
1-2
1-3
14
1-5
1-6
1-7
2-1
2-2
2-3
3-1
3-2
3-3
34
3-5
3-6
4-1
4-2
4-3
5-1
5-2
5-3
54
5-5
5-6
5-7
5-8
5-9
5-10
5-11
6-1
6-2
6-3
64
6-5
6-6
6-7
Illustrations
ILLUSTRATIONS
Title
Page
Number
Block Diagram ....................................................................................................... 1-3
Block Diagram-Internal Data Paths ..................................................................... 1-7
Cache Unit Organization ...................................................................................... 1-14
System Interface ................................................................................................... 1-15
PowerPC 604 Microprocessor Signal Groups ...................................................... 1-18
Programming Model-PowerPC 604 Microprocessor Registers ........................ 1-21
Pipeline Diagram .................................................................................................. 1-33
Programming Model-PowerPC 604 Microprocessor Registers .......................... 2-3
Instruction Address Breakpoint Register ............................................................... 2-9
Processor Identification Register ........................................................................... 2-9
Cache Organization ................................................................................................ 3-2
Cache Integration ................................................................................................... 3-3
Bus Interface Unit and MMU ................................................................................. 3-6
Memory Queue Organization ................................................................................. 3-7
MESI States .......................................................................................................... 3-12
MESI Cache Coherency Protocol-State Diagram (WIM = 001) ....................... 3-14
Machine Status Save/Restore Register 0 ................................................................ 4-6
Machine Status Save/Restore Register 1 ................................................................ 4-6
Machine State Register (MSR) .............................................................................. 4-7
MMU Conceptual Block Diagram-32-Bit Implementations ............................... 5-6
PowerPC 604 Microprocessor IMMU Block Diagram .......................................... 5-7
PowerPC 604 Microprocessor DMMU Block Diagram ........................................ 5-8
Address Translation Types ................................................................................... 5-10
General Flow of Address Translation (Real Addressing Mode and Block) ........ 5-13
General Flow of Page and Direct-Store Interface Address Translation ............... 5-15
Segment Register and DTLB Organization ......................................................... 5-25
Page Address Translation Flow-TLB Hit .......................................................... 5-28
Primary Page Table Search .................................................................................. 5-31
Secondary Page Table Search Flow ..................................................................... 5-32
Direct-Store Segment Translation Flow ............................................................... 5-37
PowerPC 604 Microprocessor Block Diagram Showing Data Paths ..................... 64
GPR Reservation Stations and Result Buses .......................................................... 6-5
Pipeline Diagram .................................................................................................... 6-6
PowerPC 604 Microprocessor Pipeline Stages ...................................................... 6-7
Instruction Fetch Address Generation .................................................................... 6-8
Data Caches and Memory Queues ....................................................................... 6-14
Instruction Timing--Cache Hit ............................................................................ 6-19
xv