Data Transfer Termination - IBM PowerPC 604 User Manual

The 604 transfers data in either single- or four-beat burst transfers. Single-beat operations
can transfer from one to eight bytes at a time and can be misaligned; see Section 8.3.2.4,
"Effect of Alignment in Data Transfers." Burst operations always transfer eight words and
are aligned on eight-word address boundaries. Burst transfers can achieve significantly
higher bus throughput than single-beat operations.
The
type
of transaction initiated by the 604 depends on whether the code or data is
cacheable and, for store operations whether the cache is considered in write-back or write-
through mode, which software controls on either a page or block basis. Burst transfers
support cacheable operations only; that is, memory structures must be marked as cacheable
(and write-back for data store operations) in the respective page or block descriptor to take
advantage of burst transfers.
The 604 output TBST indicates
to
the system whether the current transaction is a single- or
four-beat transfer (except during eciwx/ecowx transactions, when it signals the state of
EAR[28]). A burst transfer has an assumed address order. For load or store operations that
missed in the cache (and are marked as cacheable and, for stores, write-back in the
MMU),
the 604 uses the double-word-aligned address associated with the critical code or data that
initiated the transaction. This minimizes latency by allowing the critical code or data to be
forwarded to the processor before the rest of the cache line is filled. For all other burst
operations, however, the Cil(;he line write operations are transferred beginning with the oct-
word-aligned data, and burst reads begin on double-word boundaries.
The 604 does not directly support dynamic interfacing to subsystems with less than a 64-
bit data path (except for direct-store operations discussed in Section 8.6, "Direct-Store
Operation").
8.4.4 Data Transfer Termination
Four signals are used to terminate data bus transactions-TA, DRTRY (data retry), TEA
(transfer error acknowledge), and ARTRY. The TA signal indicates normal termination of
data transactions. It must always be asserted on the bus cycle coincident with the data that
it is qualifying. It may be withheld by the slave for any number of clocks until valid data is
ready to
be
supplied or accepted. DRTRY indicates invalid read data in the previous bus
clock cycle. DRTRY extends the current data beat and does not terminate it If it is asserted
after the last (or only) data beat, the 604 negates 'DBB'but still considers the data beat active
and waits for another assertion of TA. DRTRY is ignored on write operations. TEA
indicates a nonrecoverable bus error event. Upon receiving a final (or only) termination
condition, the 604 always negates DBB for one cycle, except when
data
streaming in fast-
L2/data streaming mode.
If DRTRY is asserted by the memory system to extend the last (or only) data beat past the
negation of DBB, the memory system should three-state the data bus on the clock after the
final assertion of TA, even though it will negate DRTRYon that clock. This is to prevent a
potential momentary data bus conflict if a write access begins on the following cycle.
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PowerPC 604 RISC Microprocessor User's Manual