Event Counting - IBM PowerPC 604 User Manual

Table 9-4.
MMCRO Bit Settings (Continued)
Bh
Name Description
7-8 RTCSELECT
64-blt time base, bit selection enable.
00 Pick bit 63 to count
01 Pick bit 55 to count
10
Pick
bit
51 to
count
11
Pick bit 47 to count
9
INTONBITTRANS
Cause interrupt signaling on bit transition (identifl8d in RTCSELECT) from off to
on.
0 Do
not
allow interrupt signal if chosen
bit
transitions.
1
Signal interrupt if chosen bit transitions.
Software is responsible for
setting
and clearing INTONBITTRANS.
10-15 THRESHOLD Threshold value. All 6 bits are supported by the 604 processor; allowing threshold
values from O to 63. The intent of the THRESHOLD support
Is
to be able to
characterize L 1 data cache misses.
16 PMC11NTCONTROL Enable interrupt signaling due to PMC1 counter negative.
0
Disable PMC1 interrupt signaling due to PMC1 counter negative.
1 Enable PMC1 Interrupt signaling due to PMC1 counter negative.
17 PMC21NTCONTROL Enable interrupt signaling due to PMC2 counter negative. This signal overrides
the setting of DISCOUNT.
0
Disable PMC2 interrupt signaling due to PMC2 counter negative.
1
Enable PMC2 Interrupt signaling due to PMC2 counter negative.
18 PMC2COUNTCTL May be used to trigger counting
of
PMC2 alter PMC1 has become negative or
after a perfonnance monitor interrupt is signaled.
0 Enable PMC2 counting
1
Disable PMC2 counting until PMC1
bit O Is
set or unto a performance monitor
interrupt is signaled.
This signal can be used to trigger counting of PMC2 after PMC1 has become
negative. This provides a triggering mechanism for counting after a certain
condition occurs or after a preset time
has
elapsed. It can be used to
lq)pOrt
getting the count associated with a specific event.
19-25 PMC1SELECT PMC1 input selector, 128 8V8nts selectable; 25 defined. See Table 9-2.
26-31 PMC2SELECT
PMC2 input selector, 64 events selectable; 21 defined. See Table 9-3.
9.1.2 Event Counting
Counting can
be
enabled if conditions in the processor state match a software-specified
condition. Because a software task scheduler may switch a processor's execution among
multiple processes and because statistics on only a particular process may
be
of interest, a
facility is provided to mark a process. The performance monitor
(PM)
bit, MSR[29] is used
for this purpose. System software may set this bit when a marked process is running. This
enables statistics to
be
gathered only during the execution of the marked process. The states
of MSR[PR] and MSR[PM] together define a state that the processor (supervisor or
program) and the process (marked or unmarked) may be in at any time.
If
this state matches
a state specified by the MMCR, the state for which monitoring is enabled, counting is
enabled.
9-8
Pow•PC 604 RISC Microprocessor Ueer'e Manual