Floating-Point Unit Instruction Timings - IBM PowerPC 604 User Manual

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Figure 6-15. MCIU Block Diagram
Most instructions that execute in the MCIU can finish execution and complete in the same
cycle. These include the following:
• Integer divide, multiply when OE = 0
• All mfspr instructions
• All mtspr instructions except when LR/CTR is involved
Note that all instructions that execute in the MCIU can complete during the same cycle in
which they finish executing except for the following:
• Instruction that changes OV or CA (OE= 1)
• The move to CTR/LR instructions cannot because they are not execution-serialized
6.5.3 Floating-Point Unit Instruction Timings
The floating-point unit on the 604 executes all floating-point instructions. Execution of
most floating-point instructions is pipelined within the FPU, allowing
up
to three
instructions to be executing in the FPU concurrently. While most floating-point instructions
execute with three-cycle latency and one-cycle throughput, three instructions (fdivs, fdiv,
and fres) execute with latencies of 18 to 33 cycles. The fdivs, fdiv, fres, mtfsbO, mtfsbl,
mtfsfi, mtTs, and mtfsf instructions block the floating-point pipeline until they complete
execution and thereby inhibit the execution of additional floating-point instructions. With
the exception of the mcrfs instruction, all floating-point instructions immediately forward
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Instruction Timing 6-37
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