Timing Examples - IBM PowerPC 604 User Manual

8.5
Timing Examples
This section shows timing diagrams for various scenarios. Figure 8-16 illustrates the fastest
single-beat reads possible for the 604. This figure shows both minimal latency and
maximum single-beat throughpuL By delaying the data bus tenure, the latency increases,
but, because of split-transaction pipelining, the overall throughput is not affected unless the
data bus latency causes the fourth address tenure to be delayed.
Note that all bidirectional signals are three-stated between bus tenures.
8-32
1112 31415
6
I
7
I
a
I
9
I
10 11 12
'BR
l\_.W
I \ .....
_,,~
_....,...../ \ ..... ._ _ __,/ I \'-.....
~.-----...-.....-----1
m~~~'-~~~=~~~~A~ 1 ~b~~=~~~~A~ 1 ~ 1=~~~=~~~
TPn'I'
t - - 1
--+---
,...--1--..
~
l\DD
I
\----~'
i \....._ __ _,, i \....._ __
...J,
T§'
I I I I I
AO-A311-I
-+l-<.._~c_ru_A....,.....)---+--{~-c-Pu_A--1}--+--{-acru;jj'AA~--l.l---1..-~
I I I I I
TIO-TT4 I I
Read
}-+--{
Read }-H,--"RR;;;;eadd
l--11--L.-....1
I I I I I
Te§T1 I I I I
um:
' . :::::::ftr:::!::::td
~
' .
k:::::::!::::::H
~
' .
h:H:~:::::d
' .
~
k:r!::;:::::::::::::::::::i:::::::::::r:r:(
~,
ARTRYl1---+--+---+--+--1---+---+---+--+--.i.---1---1
I I
rnm
l::t:::::=:!:::' : ::;:::{:\ b;::::::::::::rt::::::::::::::::;::\ b:::::::::@:::=::::=::::::/::::;:\
b::::::::::;::::::::t:::::::::::::n:::::::::;:::\=:::t:::=::n=::' : )
I
I
I I
I I
I
I
I I
t>lm
I I I
I I I I
I I
D0-063
lt---t--+--t~>--+--+-1 -<~>--+--+-I -t~t--1-----+--1
I I I I I I I I I I
TJS;
p::::::::::::::::::::=:::::::::::::=:::::::::::::::::\
I
p::::::::::::::::::::' : ' : ' : ::::' : :::::::::;\
I #::::=\:::::::::::::::::::::::::::::::\ I
/' : :::::::/::::::::::::::::::::::::::::::::::::::::::::j
15RTRV~l_.....__..._
__ ._____.. _
_.__.....__~1_
.......... 1 _.....__......____..._____.
I I I
TEA~l--1--..._--1--__..--4---1--•l--1-I
_ .........
_..._--''------l
I I I
I
1
2 I 3 I 4 I
s
I 6
7 1
a
I
9
I
10 11 12
Figure 8·16. Fastest Single-Beat Reads
PowerPC 604 RISC Microprocessor User's Manual