Operation Of The Instruction And Data Caches - IBM PowerPC 604 User Manual

used cache lines are written to memory after a cache miss, and cache-line snoop push-out
operations when a modified cache line experiences a snoop hit from another bus master.
Figure 8-1 shows the address path from the execution units and instruction fetcher, through
the translation logic to the caches and system interface logic.
The 604 uses separate address and data buses and a variety of control and status signals for
performing reads and writes. The address bus is 32 bits wide and the data bus is 64 bits
wide. The interface is synchronous-all 604 inputs are sampled at and all outputs are driven
from the rising edge of the bus clock. The bus can run at the full processor-clock frequency,
or at 1/2, 1/3 or 2/3 the frequency of the processor clock. While the 604 operates at
3.3 Volts, all the
1/0
signals are 5.0-Volt TTL-compatible.
8.1.1 Operation of the Instruction and Data Caches
The 604 provides independent instruction and data caches. Each cache is a physically-
addressed, 16-Kbyte cache with four-way set associativity. Both caches consist of 128 sets
of four cache lines, with eight words in each cache line.
Because the data cache on the 604 is an on-chip, write-back primary cache, the predominant
type of transaction for most applications is burst-read memory operations, followed by
burst-write memory operations, direct-store operations, and single-beat (noncacheable or
write-through) memory read and write operations. Additionally, there can be address-only
operations, variants of the burst and single-beat operations (global memory operations that
are sno9ped, and atomic memory operations, for example), and address retry activity (for
example, when a snooped read access hits a modified line in the cache).
The 604 data cache tags are dual-ported to facilitate efficient coherency checking. This
allows data cache accesses to occur concurrently with snooping operations. Data cache
accesses are only interrupted when the snoop control logic detects a situation where snoop
push of modified data is required to maintain memory coherency.
The 604 supports a four-state coherency protocol that supports the modified, exclusive,
shared and invalid (MESI) cache states. The MESI protocol ensures that the 604 operates
coherently in systems that contain multiple four-state caches, provided that all bus
participants employ similar snooping and coherency control mechanisms.
Cache lines in the 604 are loaded in four beats of 64 bits each. The burst load is performed
as critical-double-word-first. The cache that is being loaded allows internal accesses until
the load completes (that is, the 604 supports cache hits under misses). The critical double
word is simultaneously written to the cache and forwarded to the requesting unit, thus
minimizing stalls due to load delays. If consecutive double words are required from the
same cache line following a cache line miss, the LSU stalls until the entire cache line has
been loaded into the cache,
8-2
PowerPC 604 RISC Microprocessor User's Manual