IBM PowerPC 604 User Manual page 204

Address Translation with
Segment Descriptor
Use EAO-EA3 to
Select One ol 16 On-Chip
Segment Registers
Check T bit in
Segment Descriptor
Page Address
Translation
Direct-Store
Segment Address
(T
=
1)'
~(T=O)
othe~~
Perform Direct-Store
Segment Translation
l
I-Fetch with N bit Set in
Segment Descriptor
(No-Execute)
Generate 52-Bit VH1ual
Address from Segment
Descriptor
Compare Virtual
Address with TLB
Entries
L - - - - - - . J
TLB
Miss
.....
.....
.....
.....
'""' TLB
Hit • ...._
..... .....
(See Figure 5-8)
Perform Page Table
Search Operation
(See
Figure 5-9)
..... .....
..... .....
PTENot
Found
PTE Found
r -
_I_ - ,
Access
Permitted
Translate Address
Continue Access
to Memory Subsystem
(See Th6 Programming
Environments Manual}
Access
Protected
Access Faulted
Load TLB Entry
L - - - - . J
Access Faulted
- - - Optional to the PowerPC architecture. Implemented In the 604.
*Not allowed for
instruction accesses
(causes ISi exception)
Figure S-6. General Flow of Page and Direct-Store Interface Address Translation
Chapter 5. Memory Management
5-15