Page Table Updates - IBM PowerPC 604 User Manual

If
the MMU registers are being accessed by an instruction in the instruction stream, the
IMMU stalls for one translation cycle to perform those operation. The sequencer serializes
instructions to ensure the data correctness. For updating the IBATs and SRs, the sequencer
classifies those operations as fetch serialization. After such an instruction is dispatched, the
instruction buffer is flushed and the fetch stalls until the instruction completes. However,
for reading from the IBATs, the operation is classified as execution serialization.
As
long as
the LSU ensures that all previous instructions can be executed, subsequent instructions can
be
fetched and dispatched.
5.4.6 Page Table Updates
This section describes the requirements on the software when updating page tables in
memory via some pseudocode examples. Multiprocessor systems must follow the rules
described in this section so that all processors operate with a consistent set of page tables.
Even single-processor systems must follow certain rules, because software changes must
be synchronized with the other instructions in execution and with automatic updates that
may
be
made by the hardware (referenced and changed bit updates). Updates
to
the tables
include the following operations:
• Adding a PI'E
• Modifying a PTE, including modifying the R and C bits of a PI'E
• Deleting a PI'E
PI'Es must be locked on multiprocessor systems. Access to PI'Es must be appropriately
synchronized by software locking of (that is, guaranteeing exclusive access to) PI'Es or
PI'EGs if more than one processor can modify the table at that time. In the examples below,
'lockO' and 'unlock()' refer to software locks that must be performed
to
provide exclusive
access to the PI'E being updated. See Appendix E, "Synchronization Programming
Examples,'' in The Programming Environments Manual, for more information about the
use of the reservation instructions (such as the lwarx and stwcx. instructions)
to
perform
software locking.
On single-processor systems, PI'Es need not be locked. To adapt the examples given below
for the single-processor case, simply delete the 'lock()' and 'unlock()' lines from the
examples. The sync instructions shown are required even for single-processor systems (to
ensure that all previous changes to the page tables and all preceding tlbie instructions have
completed).
When TLBs are implemented, they are defined as noncoherent caches of the page tables.
TLB entries must be invalidated explicitly with the TLB invalidate entry instruction (tlbie)
whenever the corresponding PI'E is modified. In a multiprocessor system, the tlbie
instruction must be controlled by software locking, so that the tlbie is issued on only one
processor at a time. The sync instruction causes the processor to wait until the TLB
invalidate operation in progress by this processor is complete.
Chapter 5. Memory Management
5-33