IBM PowerPC 604 User Manual page 122

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Table 2-46. Translatlon Lookaslde Buffer Management Instruction
Name Mnemonic
Operand
Implementation Notes
Syntax
TLB tibia rB
Execution of this instruction causes all entries in the congruence class
Invalidate corresponding to the specified EA to be invalidated in the processor
Entry
executing the Instruction and In the other processors attached to the
same bus by causing a TLB Invalidate operation on the bus as
described in Section 7.2.4, "Address Transfer Attribute Signals."
The OEA requires that a synchronization instruction be issued to
guarantee completion of a tibia across all processors of a system.
The 604 implements the tlbsync instruction which causes a
TLBSYNC operation to appear on the bus as a distinct operation,
different from a SYNC operation. It is this bus operation that causes
synchronization of snooped tibia instructions. Multiple tibia
instructions can be executed correctly with only one tlbsync
instruction, following the last tibia, to guarantee an previous tibia
instructions have been perfonned globaOy.
Software must ensure that Instruction fetches or memory references
to the virtual pages specified by the tibia have been completed prior
to executing the tibia instruction.
When a snooping 604 detects a TLB invalidate entry operation on the
bus,
it
accepts the operation only if no TLB invalidate entry operation
is being executed by this processor and an processors on the bus
accept the operation
(AFffFIV
is not asserted). Once accepted, the
TLB invalidation is performed unless the processor is executing a
multiple/string instruction, in which case the TLB invaHdation is
delayed until it has completed.
Other than the possible TLB miss on the next instruction pref etch, the
tibia does not affect the instruction fetch operation-that is, the
p!'efetch buffer is not purged and does not cause these instructions to
be refetched.
TLB
tlbsync
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The TLBSYNC operation appears on the bus as a distinct operation,
Synchronize different from a SYNC operation. It is this bus operation that causes
synchronization of snooped tlble instructions.
See the tibia
de~ion
above for information regrading using the
tlbsync instruction with the tlble instruction. For more inlonnation
about how other processors react to TLB operations broadcast on the
system bus of a multiprocessing system, see Section 3.9.6, "Cache
Reaction to Specific Bus Operations.•
Implementation Note-The tibia instruction is optional for an implementation if its
effects can be achieved through some other mechanism. As described above, the tlbie
instruction can be used to invalidate a particular index of the TLB based on EA[14-19].
With that concept in mind, a sequence of 64 tlbie instructions followed by a single tlbsync
instruction would cause all the 604 TLB structures
to
be invalidated (for EA[14-19]
=
0, 1,
2, ... , 63). Therefore the tibia instruction is not implemented on the 604. Execution of a tibia
instruction causes an illegal instruction program exception.
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PowerPC 604 RISC Micropr0C8880r User's Manual