IBM PowerPC 604 User Manual page 353

8.6.2.1 Packet O
Figure 8-23 shows the organization of the first packet in a direct-store transaction.
The XATC contains the 1/0 opcode, as discussed earlier
and
as shown in Table 8-8. The
address bus contains the following:
Key bit II segment register II sender tag
A(0-31)+Atbibutes ~
--~~~~~~~~~~-A--~~~~~~~~--
r
Address Bus (AO-A31) \
0 7 0 1 2 3 1112 27 28 31
1,.....-.,..,.XA=r=c--.I
+
I II I I I
l/OOpcode
~
Ly-J
l ~
l
L \....
B BUI IDD - - . / PIO
From Segm!nt Register
Key Bit
Reserved
Figure 8-23. Direct-Store Operation-Packet
O
This information is organized as follows:
• Bits 0 and 1 of the address bus are reserved-the 604 always drives these bits
to
zero.
• Key bit-Bit 2 is the key bit from the segment register (either SR[Kp] or SR[Ks]).
Kp indicates user-level access and Ks indicate supervisor-level access. The 604
multiplexes the correct key bit into this position according to the current operating
context (user or supervisor). (Note that user- and supervisor-level refer to problem
and privileged state, respectively, in the architecture specification.)
• Segment register-Address bits 3-27 correspond
to
bits 3-27 of the selected
segment register. Note that address bits 3-11 form the 9-bit receiver tag. Software
must initialize these bits in the segment register to the ID of the BUC
to
be
addressed; they are referred
to
as the BUID (bus unit ID) bits.
• PID (sender tag)-Address bits 28-31 form the 4-bit sender tag. The 604 PID
(processor ID) comes from bits 28-31 of the 604's processor ID register. The 4-bit
PID tag allows a maximum of 16 processor IDs
to be
defined for a given system. ff
more bits are needed for a very large multiprocessor system, for example, it is
envisioned that the second-level cache (or equivalent logic) can append a larger
processor tag as needed. The BUC addressed by the receiver tag should latch the
sender address required by the subsequent 1/0 reply operation.
Chapter 8. System Interface Operation