Effect Of Artry Assertion On Data Transfer And Arbitration - IBM PowerPC 604 User Manual

be an outstanding data bus transaction when a new address transaction is retried. In this
case, the 604 becomes the data bus master to complete the previous transaction.
8.4.1.1 Effect of ARTRY Assertion on Data Transfer and Arbitration
The system designer must define the qualified snoop response window, and ensure that data
is not transferred prior to one cycle before the end of that window in non-fast-L2/data
streaming mode, or prior to the same cycle as the end of that window in fast-L2/data
streaming mode. The 604 supports a snoop response window as early as two cycles after
assertion of TS. Operation of the 604 in fast-L2/data streaming mode requires that data be
transferred no earlier than the first cycle of the ARTRY window, not the cycle earlier. The
system may assert TA for a data transaction prior to the termination of an address tenure;
in this case note that the snoop response window is closed either on the clock that TA is
asserted (if in fast-L2/data streaming mode), or the clock after the assertion of TA (if in
non-fast-L2/data streaming mode).
An asserted ARTRY can invalidate a previous or current data transfer and terminate the
data cycle, invalidate a qualified data bus grant, or cancel a future data transfer. The
possible scenarios are described below:
• If data is transferred (via assertion of TA) two or more cycles before the beginning
of the snoop window in non-fast-L2/data streaming mode, or one or more cycles
before the beginning of the snoop window in fast-L2/data streaming, then data is
transferred too early to be cancelled by ARTRY. Therefore, systems in which
ARTRY can be asserted must not attempt data transfers (assert TA) prior to this
cycle.
• If data is transferred in the cycle before the beginning of the snoop response window,
assertion of ARTRY invalidates the data transfer, in a similar fashion to assertion of
DRTRY, except that the data tenure is aborted, not extended If the fast-L2/data
streaming mode is active, data may not be transferred in this cycle.
• If data is transferred in the first cycle of the snoop response window, assertion of
ARTRY invalidates the data transfer. This is similar to deasserting TA except that
the data tenure is aborted, instead of continued.
• If DBG has been asserted, the system must not attempt to transfer data in cycles
following the assertion of ARTRY. The 604 negates DBB the cycle following
ARTRY, and expects no more data to be transferred. However, note that the data
related to a previous address tenure must not be affected, and that the system must
distinguish this case.
• If a DBG has not been asserted, an ARTRY assertion effectively negates the implied
data bus request that was associated with the address transfer, and the 604 will not
expect a transfer. The system must not assert DBG for this transfer if any other 604
data transfers are pending.
• If ARTRY assertion occurs while a data transfer is in progress, the 604 will
terminate data transfers following the first cycle of ARTRY assertion. This means
that a burst transfer may be cut short.
Chapter 8. System Interface Operation
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