Sia And Sda Registers; Sampled Instruction Address Register (Sia); Sampled Data Address Register (Sda); Updating Sia And Sda - IBM PowerPC 604 User Manual

9.1.1.2 SIA and SDA Registers
The two address registers contain the addresses of the data or the instruction that caused a
threshold-related performance monitor interrupt For more information on
threshold-related interrupts, see Section 9.1.2.2, "Threshold Events."
9.1.1.2.1 Sampled Instruction Address Register {SIA)
The SIA contains the effective address of an instruction executing at or around the time that
the processor signals the performance monitor interrupt condition. If the performance
monitor interrupt was triggered by a threshold event, the SIA contains the exact instruction
that caused the counter to become negative. The instruction whose effective address is put
in the SIA is called the sampled instruction.
If the performance monitor interrupt was caused by something besides a threshold event,
the SIA contains the address of the last instruction completed during that cycle. The SDA
contains an effective address that is not guaranteed to match the instruction in the SIA. The
SIA and SDA are supervisor-level SPRs.
The SIA can be read by using the mfspr instruction and written to by using the mtspr
instruction (SPR 955).
9.1.1.2.2 Sampled Data Address Register (SDA)
The SDA contains the effective address of an operand of an instruction executing at or
around the time that the processor signals the performance monitor interrupt condition. In
this case the SDA is not meant to have any connection with the value in the SIA. If the
performance monitor interrupt was triggered by a threshold event, the SDA contains the
effective address of the operand of the SIA.
If the performance monitor interrupt was caused by something other than a threshold event,
the SIA contains the address of the last instruction completed during that cycle. The SDA
contains an effective address that is not guaranteed to match the instruction in the SIA. The
SIA and SDA are supervisor-level SPRs.
The SDA can be read by using the mfspr instruction and written to by using the mtspr
instruction (SPR 959).
9.1.1.2.3 Updating SIA and SDA
The values of the SIA and SDA registers depend on the type of event being monitored.
These registers have predicted values after a PMI is signaled. A PMI may be signaled, but
not serviced because the exception is masked by the MSR(EE) bit. Programmers must
make sure that this bit is set active in order to take the PMI.
9.1.1.3 Monitor Mode Control Register O (MMCRO)
The monitor mode control register 0 (MMCRO) is a 32-bit SPR (SPR 952) whose bits are
partitioned into bit fields that determine the events to be counted and recorded. The
selection of allowable combinations of events causes the counters to operate concurrently.
Control fields in the MMCRO select the events to be counted, can enable a counter overflow
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PowerPC 604 RISC Microprocessor User's Manual