Data Bus Write Only; Data Transfer - IBM PowerPC 604 User Manual

memory system can track the start and end of the data tenure.
In
non-fast-L2/data
streaming mode, if DBB is not used to signal the end of a data tenure, DBG is only asserted
to the next bus master the cycle before the cycle that the next bus master may actually begin
its data tenure, rather than asserting it earlier (usually during another master's data tenure)
and allowing the negation of DBB to be
the
final gating signal for a qualified data bus granL
If the 604 is in fast-L2/data streaming mode, the DBB signal is an output only, and is not
sampled by the 604. Even if DBB is ignored in the system, the 604 always recognizes its
own assertion of DBB (except when in fast-L2/data streaming mode), and requires one
cycle after data tenure completion
to
negate its own DBB before recognizing a qualified
data bus grant for another data tenure. If the DBB signal is not used by
the
system, DBB
must still be connected to a pull-up resistor on the 604 to ensure proper operation. If the
604 is in fast-L2/data streaming mode, and data streaming is
to
be performed across
multiple processors,
the
DBB signal for each processor should be connected directly
to
the
memory arbiter.
8.4.2 Data Bus Write Only
As a result of address pipelining, the 604 may have up to three data tenures queued to
perform when it receives a qualified DBG. Generally, the data tenures should be performed
in strict order
(the
same order) as their address tenures were performed.
The
604, however,
also supports a limited out-of-order capability with
the
data bus write only (DBWO) input.
The DBWO capability exists to alleviate deadlock conditions that are possible in certain
system topologies. When recognized on the clock of a qualified DBG, DBWO may direct
the
604
to
perform
the
next pending data write tenure even if a pending read tenure would
have normally been performed firsL For more information on the operation of DBWO, refer
to Section 8.11, "Using Data Bus Write Only."
If the 604 has any data tenures
to
perform, it always accepts data bus mastership to perform
a data tenure when it recognizes a qualified DBG. If DBWO is asserted with a qualified
DBG and no write tenure is queued to
run,
the 604 still takes mastership of the data bus to
perform
the
next pending read data tenure. If the 604 has multiple queued writes, the
assertion of DBWO causes the reordering of the write operation whose address was sent
first.
Generally, DBWO should only be used
to
allow a copy-back operation (burst write) to
occur before a pending read operation. If DBWO is used for single-beat write operations,
it may negate
the
effect of
the
eieio instruction by allowing a write operation
to
precede a
program-scheduled read operation. If DBWO is asserted when the 604 does not have write
data available, bus operations occur as if DBWO had not been asserted.
8.4.3 Data Transfer
The data transfer signals include DHO-DH31, DLO-DL31, DPO-DP7 and DPE. For
memory accesses, the DH and DL signals form a 64-bit data path for read and write
operations.
Chapt• 8.
System
Interface Operation 8-23